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PI90LVT14

1:5 Clock Distribution

Pericom Semiconductor 

PI90LV14/PI90LVT14

1:5 Clock Distribution 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122

Switching Characteristics over Recommended Operating Conditions (unless otherwise noted)(8,9).

Characteristic

Symbol Min.

Typ.

Max.

Units Condition

Propagation Delay to Output

CLK to CLKOUT ±

SCLK to CLKOUT ±

SEL to CLKOUT ±

tPLH

tPHL

3.0

2.5

4.0

3.5

ns

2.6

3.6

Disable Time

CLK or SCLK to CLKOUT ±

Part-to-Part Skew

CLK (Diff) to Q

CLK (SE), SCLK to Q

With Device Skew

Cycle-to-Cycle Jitter

Period Jitter

Setup Time

ENx to CLK

CEN to CLK

Hold Time

ENx, CEN to SCLK

ENx, CEN to CLKx

Minimum Input Swing (CLK)

Com. Mode Range (CLK)

Rise/Fall Times (20 – 80%)

SCLK to CLKOUT±

SCLK to CLKOUT±

Duty Cycle Distortion Pulse Skew ( tPLH - tPHL)

Channel-to-Channel Skew, same edge

Maximum Operating Frequency

tPHZ

tPLZ

tPZH

tPZL

tskew

tskew

tskew

tjit(cc)

tjit(per)

ts

ts

th

th

VPP

VCMR

tr

tf

tSK1R

tSK2R

–50

–22

100

100

0.20

0.125

150

150

2.7

3.5

2.7

3.5

ns

4.7

6.0

3.7

6.0

TBD

TBD

TBD

+50

+22

ps

–100

–100

550

720

500

720

0.800

V

1.5

VCC - 0.20

1200

1200

ps

200

300

70

190

250

MHz

2

1

Figure 6

Figure 7

2

2

3

4

5

6

7

Notes:

1. Within-Device skew is defined for identical transitions on similar paths through a device.

2. Setup, Hold, and Disable times are all relative to a falling edge on CLK or SCLK.

3. Minimum input swing for which AC parameters are guaranteed. Full DC LVDS output swings will be generated with only 50mV

input swings.

4. The range in which the high level of the input swing must fall while meeting the VPP spec.

5. tSKIR is the difference in receiver propagation delay (tPLH-tPHL) of one device, and is the duty cycle distortion of the output at

any given temperature and VCC. The propagation delay specification is a device-to-device worst case over process, voltage, and

temperature.

6. tSK2R is the difference in receiver propagation delay between channels in the same device of any outputs switching in the same

direction. This parameter is guaranteed by design and characterization.

7. Generator input conditions: trtf < 1ns, 50% duty cycle, differential (1.10V to 1.35V peak-peak).

Output Criteria: 60%/40% duty cycle, VOL (max) 0-4V, VOH (min) 2.7V, Load - 7pF (stray plus probes).

8. CL includes probe and fixture capacitance.

9. Generator waveform for all tests unless otherwise specified: f = 25 MHz, ZO = 50 ohms, tr = 1ns, tf = 1ns (35%-65%). To ensure fastest

propagation delay & minimum skew, clock input edge rates should not be slower than 1ns/V; control signals not slower than 3ns/V.

3

PS8538A 09/11/01

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