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STV9432TAP

100MHz OSD FOR MONITOR INCLUDING BEAM CURRENTS, VIDEO TIMING ANALYZER AND PWMs

STMicroelectronics 

STV9432TAP

6 - TIMINGS

Symbol

Parameter

Min. Typ. Max.

Unit

OSCILLATOR

fOSC

Clock Frequency

fPXL

Maximum Pixel Frequency

R, G, B, FBLK (CLOAD = 30pF)

tR

Rise Time (see Note 1)

tF

Fall Time (see Note 1)

tSKEW

Skew between R, G, B, FBLK

I2C INTERFACE: SDA AND SCL (see Figure 1)

8

100

5

5

5

MHz

MHz

ns

ns

ns

fSCL

tBUF

tHDS

tSUP

tLOW

tHIGH

tHDAT

tSUDAT

tF

tR

SCL Clock Frequency

Time the bus must be free between 2 access

Hold Time for Start Condition

Set up Time for Stop Condition

The Low Period of Clock

The High Period of Clock

Hold Time Data

Set up Time Data

Fall Time of SDA

Rise Time of both SCL and SDA

0

400

kHz

500

ns

500

ns

500

ns

400

ns

400

ns

0

ns

500

ns

20

ns

Depend on the pull-up resistor and the

load capacitance

ANALYZER (HS, HFLY, AV)

tHLOW

tHHIGH

Hs

Low Pulse Width (see Note 3)

High Pulse Width

Hs Frequency

2

4091

tHTIM

2

4091

tHTIM

Hfly

ANALYZER (VS)

tVLOW

tVHIGH

Low Pulse Width

High Pulse Width

2

4091

Lines

2

4091

Lines

Notes:

- These parameters are not tested on each unit. They are measured during our internal qualification procedure which

includes characterization on batches coming from corners of our processes and also temperature characterization.

- The ADC measurements are dependant on the noise. The test is done by correlation in order to screen out marginal

devices.

- tHTIM = 3tOSC : 40.

Figure 1.

SDA

STOP START

tBUF

tHDS

SCL

DATA

tHDAT

tSUDAT

tHIGH

tLOW

STOP

tSUP

6/25

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