LTC1390CS Ver la hoja de datos (PDF) - Linear Technology

Número de pieza

componentes Descripción

Lista de partido

LTC1390CS

8-Channel Analog Multiplexer with Serial Interface

Linear Technology 

LTC1390

PIN FUNCTIONS

CS (Pin 11): Chip Select Input (TTL/CMOS Compatible). A

logic high on this input enables LTC1390 to read in the

channel selection bits and allow data transfer from Data 1

to Data 2. A logic low enables the desired channel for

analog signal transmission and allows data transfer from

Data 2 to Data 1.

Data 1 (Pin 12): Bidirectional Digital Input/Output (TTL/

CMOS Compatible). Input for the channel selection bits.

Data 2 (Pin 13): Bidirectional Digital Input/Output (TTL/

CMOS Compatible).

V – (Pin 14): Negative Supply. For ±5V dual supply appli-

cations, |V–| should not exceed |V +| by more than 20% for

proper channel selection.

D (Pin 15): Analog Multiplexer Output/Analog

Demultiplexer Input.

V+ (Pin 16): Positive Supply.

UU W U

APPLICATIO S I FOR ATIO

Multiplexer Operation

Figure 1 shows the block diagram of the components

within the LTC1390 required for MUX operation. The

LTC1390 uses Data 1 to select its 8 channels and a chip

select input CS to switch on the selected channel as shown

in Figure 2.

CLK

DATA 1

CS

CONTROL

LOGIC

4-BIT SHIFT

REGISTER

ANALOG

INPUT

MUX

BLOCK

ANALOG

OUTPUT

LTC1390 • F01

Figure 1: Simplified Block Diagram of the MUX Operation

When CS is high, the input data on the Data 1 pin is latched

into the 4-bit shift register on each rising clock edge. The

input data consists of an “EN” bit and a string of three bits

for channel selection. If “EN” bit is logic high as illustrated

in the first input data sequence, it enables the selected

channel. To ensure correct operation, the CS must be

pulled low before the next rising clock edge.

Once the CS is pulled low, all channels are simultaneously

switched off to ensure a break-before-make interval. After

a delay of tON, the selected channel is switched on allowing

signal transmission. The selected channel remains on

until the next falling edge of CS, and after a delay of tOFF,

it terminates the analog signal transmission and subse-

quently allows the selection of the next channel. If “EN” bit

is logic low, as illustrated in the second data sequence, it

disables all channels and there will be no analog signal

CLK

CS

DATA 1

EN = HIGH

B2

B1 B0

EN = LOW

B2 B1 B0

ANY

ANALOG

INPUTS

D

tON

tOFF

Figure 2: Multiplexer Operation

LTC1390 • F02

sn1390 1390fs

5

Share Link: