PLDC20RA10 Ver la hoja de datos (PDF) - Cypress Semiconductor

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PLDC20RA10

Reprogrammable Asynchronous CMOS Logic Device

Cypress Semiconductor 

PLDC20RA10

.

PRELOAD

(FROM PIN 1)

OUTPUT ENABLE

(FROM PIN 13)

1S

S

O

TO I/O PIN

DQ

O

C0

PL

P

R

Figure 1. PLDC20RA10 Macrocell

RA10–5

Output Always Enabled

Programmable

External Pin

OE

RA10–6

Combination of

Programmable and Hardwired

RA10–7

RA10–8

Figure 2. Four Possible Output Enable Alternatives for the PLDC20RA10

RA10–9

Document #: 38-03012 Rev. **

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