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PMB2349

Wireless Components Optimized RF/IF Dual PLL Frequency Synthesizer

Infineon Technologies 

Confidential

PMB 2349

preliminary

Functional Description

3.4.6 Fast wake-up programming

When the circuit is connected to the supply voltage all registers are undefined.

Due to the fact that each counter is loading its new start value after it is decre-

mented to „zero“, the start-up time of the counters with the programmed values

is too long for some applications. If the counters are programmed in standby

mode 2 and the PLLs are switched afterwards in operating mode, the counters

are starting immediatly with the programmed values. Therefore following data

transfer sequence is recommended:

Table 3-2 Fast Wake Up Data Transfer Sequence

Step

Serial Data Transfer Sequence

1

Long Control Word: Asynchronous Mode, Standby2

2

R-Counter

3

A-/N-Counter

4

Long Control Word: Synchronous Mode, Operating Mode

3.4.7 Phase Detector Outputs

RI

fR (RI:R)

RF1/2

fV (RF1:M)

(RF2:M)

P-Channel

CP

Tri-State

N-Channel

positive Polarity

CP

P-Channel

Tri-State

N-Channel

negative Polarity

LD

Frequency fV < fR

fV lagging

Frequency fV > fR

fV leading

The timing diagram is valid for PLL1 and PLL2.

Frequency fV = fR

lock state

Wireless Components

3 - 11

Specification, May 2000

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