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CS5331A-BS

8-Pin, Stereo A/D Converter for Digital Audio

Cirrus Logic 

CS5330A/CS5331A

Figure 4. CS5330A/31A Initialization and Power-Down Sequence

The CS5330A and CS5331A have a Power-

Down mode wherein typical consumption drops

to 0.5 mW. This is initiated when a loss of clock

is detected on either the LRCK or MCLK pins in

Slave Mode, or the MCLK pin in Master Mode.

The initialization sequence will begin when

MCLK, and LRCK for slave mode, are restored.

In slave mode power-down, the CS5330A and

CS5331A will adapt to changes in

MCLK/LRCK frequency ratio during the initia-

tilization sequence. It is recommended that

clocks not be applied to the device prior to

power supply settling. A reset circuit may be im-

plemented by gating the MCLK signal.

DS138F2

Grounding and Power Supply Decoupling

As with any high resolution converter, the ADC

requires careful attention to power supply and

grounding arrangements if its potential perform-

ance is to be realized. Figure 1 shows the

recommended power arrangements with VA+

connected to a clean +5V supply. Decoupling

capacitors should be as near to the ADC as pos-

sible, with the low value ceramic capacitor being

the nearest. To minimize digital noise, connect

the ADC digital outputs only to CMOS inputs.

The printed circuit board layout should have

separate analog and digital regions and ground

planes. An evaluation board, CDB5330A or

CDB5331A, is available which demonstrates the

optimum layout and power supply arrangements,

as well as allowing fast evaluation of the

CS5330A and CS5331A.

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