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CS5331A-BS

8-Pin, Stereo A/D Converter for Digital Audio

Cirrus Logic 

CS5330A/CS5331A

PIN DESCRIPTIONS

SERIAL DATA OUTPUT SDATA 1

SERIAL DATA CLOCK

SCLK 2

LEFT/RIGHT CLOCK

LRCK

3

MASTER CLOCK

MCLK

4

Power Supply Connections

VA+ - Positive Analog Power, PIN 7.

Positive analog supply (Nominally +5V).

8 AINL

LEFT ANALOG INPUT

7 VA+

ANALOG POWER

6 AGND ANALOG GROUND

5 AINR

RIGHT ANALOG INPUT

AGND - Analog Ground, PIN 6.

Analog ground reference.

Analog Inputs

AINL - Analog Left Channel Input, PIN 8.

Analog input for the left channel. Typically 4Vpp for a full-scale input signal.

AINR - Analog Right Channel Input, PIN 5.

Analog input for the right channel. Typically 4Vpp for a full-scale input signal.

Digital Inputs

MCLK - Master Clock Input, PIN 4.

Source for the delta-sigma modulator sampling and digital filter clock. Sample rates and digital

filter characteristics scale to the MCLK frequency.

Digital Inputs or Outputs

SCLK - Serial Data Clock, PIN 2.

SCLK is an input clock at any frequency from 32× tο 64× the output word rate. SCLK can

also be an output clock at 64× if in the Master Mode. Data is clocked out on the falling edge

of SCLK.

LRCK - Left/Right Clock, PIN 3.

LRCK selects the left or right channel for output on SDATA. The LRCK frequency must be at

the output sample rate. LRCK is an output clock if in Master Mode. Although the outputs of

each channel are transmitted at different times, the two words in an LRCK cycle represent

simultaneously sampled analog inputs.

Digital Outputs

SDATA - Audio Serial Data Output, PIN 1.

Two’s complement MSB-first serial data is output on this pin. A 47 kohm resistor on this pin

will place the CS5330A/31A into Master Mode.

DS138F2

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