Q67007-A9648 Ver la hoja de datos (PDF) - Infineon Technologies
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Q67007-A9648 Datasheet PDF : 58 Pages
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TLE 6368 / SONIC
The transmission cycle begins when the TLE 6368 G1 / SONIC is selected by the “not
chip select” input CS (H to L). After the CS input returns from L to H, the word that has
been read in at the DI line becomes the new control word. The DO output switches to
tristate status at this point, thereby releasing the DO bus circuit for other uses. For details
of the SPI timing please refer to Figures 10 to 13.
The SPI will be reset to default values given in the following table “write bit meaning” if
the RAM good flag of Q_LDO1 indicates a cold start (lower output voltage than 3.3V).
The reset will be active as long as the power on reset is present so during the reset delay
time at power up no SPI commands are accepted.
The register content of the SPI - including watchdog timings and reset delay timings - is
maintained if the RAM good flag of Q_LDO1 indicates a warm start (i.e. Q_LDO1 did not
decrease below 3.3V).
2.12.1 Write mode
The following tables show the bit assignment to the different control functions, how to
change settings with the right bit combination and also the default status at power up.
2.12.2 Write mode bit assignment
BIT
Name
Default
DO
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D 15
WD_ NOT
T1-
T2-
T6-
T4-
T5-
T6-
OFF1 assigned control control control control control control
sleep
WD_
OFF2
reset 1 reset 2
WD1
WD2
WD_
OFF3
WD_
TRIG
1
X
1
1
1
1
1
1
1
0
1
1
0
0
1
0
Figure 8 Write Bit assignment
Write Bit meaning
Function
Not assigned
Tracker 1 to 6 - control:
turn on/off the individual trackers
Power down:
send device to sleep
Data Sheet, Rev. 1.32
Bit
D1
D2
D3
D4
D5
D6
D7
D8
17
Combination
X
0: OFF
1: ON
Default
X
1
0: SLEEP
1
1: NORMAL
2004-10-15
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