EtronTech
Write Cycle3
(UB#, LB# Controlled)(See Note 4)
tWC
EM564166
Address
tAS
tW P
tWR
WE#
tCW
CE#
UB# , LB#
DO UT
DIN
tBW
tBLZ tWHZ
tLZ
(See Note 5)
tDS
tDH
VALID DATA IN
Note:
1. WE# remains HIGH for the read cycle.
2. If CE# goes LOW with or after WE# goes LOW, the outputs will remain at high impedance.
3. If CE# goes HIGH coincident with or before WE# goes HIGH, the outputs will remain at high impedance.
4. If OE# is HIGH during the write cycle, the outputs will remain at high impedance.
5. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be
applied.
Preliminary
9
Rev 1.0
May 2001