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RT9212

Dual 5V Synchronous Buck PWM DC-DC and Linear Power Controller

Richtek Technology 

RT9212

Preliminary

Vin

PWM

PWM

+

Comparator

-

VRAMP

Lo

Vout

Co

ESR

Zf

-

+

Zc

VREF

Compensator

Figure 1

Modulator Frequency Equations

The modulator transfer function is the small-signal transfer

function of VOUT/VE/A. This transfer function is dominated

by a DC gain and the output filter (LO and CO), with a double

pole frequency at FLC and a zero at FESR. The DC gain of

the modulator is the input voltage (VIN) divided by the peak-

to-peak oscillator voltage VRAMP.

The first step is to calculate the complex conjugate poles

contributed by the LC output filter.

The output LC filter introduces a double pole,−40dB/decade

gain slope above its corner resonant frequency, and a total

phase lag of 180 degrees. The Resonant frequency of the

LC filter expressed as follows :

1

FP(LC) =

2π × LO × CO

The next step of compensation design is to calculate the

ESR zero. The ESR zero is contributed by the ESR

associated with the output capacitance. Note that this

requires that the output capacitor should have enough ESR

to satisfy stability requirements. The ESR zero of the

output capacitor expressed as follows :

1

FZ(ESR) =

2π × CO × ESR

Compensation Frequency Equations

The compensation network consists of the error amplifier

and the impedance networks ZC and ZF as Figure 2 shows.

Zf

C1

R2

C2

Zc

R1

VOUT

-

EA

COMP1

+

FB1

Rf

RT9212

VREF

FP1 = 0

Figure 2

1

FZ1 =

2π × R2 × C2

1

FP1 =

2π × R2 (C1// C2)

Figure 3 shows the DC-DC converter's gain vs. frequency.

The compensation gain uses external impedance networks

ZC and ZF to provide a stable, high bandwidth loop.

High crossover frequency is desirable for fast transient

response, but often jeopardize the system stability. In order

to cancel one of the LC filter poles, place the zero before

the LC filter resonant frequency. In the experience, place

the zero at 75% LC filter resonant frequency.Crossover

frequency should be higher than the ESR zero but less

than 1/5 of the switching frequency.

The second pole be place at half the switching frequency.

80 80

Loop Gain

60

40 40

20

Compensation

Gain

00

Modulator

-20 Gain

-40-40

-60-60

110H0zvdb(vo) vdb(comp2)11000vHd0zb(lo)

11.0kKHz

110K0Hzk

FrequFreequnenccyy (Hz)

Figure 3

11000K0Hzk

1.01MHMz

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12

DS9212-05 March 2007

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