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RT9212

Dual 5V Synchronous Buck PWM DC-DC and Linear Power Controller

Richtek Technology 

Preliminary

RT9212

Reference Voltage

Because one of the RT9212 regulators uses a low 35dB

gain error amplifier, shown in Figure 4. The voltage

regulation is dependent on VIN & VOUT setting.The FB

reference voltage of 0.8V is trimmed at VIN = 5V &

VOUT = 2.5V condition. In a fixed VIN = 5V application, the

FB reference voltage vs. VOUT voltage can be calculated

as Figure 5.

R2

FB

+

-

R1

1K

REF

0.8V

56K

-

EA

+

RAMP

1.9V

+

PWM

-

Figure 4

0.815

0.81

0.805

0.8

0.795

0.79

0.785

0.78

0.775

1 1.5 2 2.5 3 3.5 4 4.5 5

VOUT (V)

Figure 5

Layout Consideration

The layout is very important when designing high frequency

switching converters. Layout will affect noise pickup and

can cause a good design to perform with less than expected

results.

1. Even though double-sided PCB is usually sufficient for

a good layout, four-layer PCB is the optimum approach to

reducing the noise. Use the two internal layers as the power

and GND planes, the top layer for power connections with

wide, copper filled areas, and the bottom layer for the noise

sensitive traces.

2. There are two sets of critical components in a DC-DC

converter. The switching components are the most critical

because they switch large amounts of energy, and therefore

tend to generate large amounts of noise. The others are

the small signal components that connect to sensitive

nodes or supply critical bypass current and signal coupling.

Make all critical component ground connections with vias

to GND plane.

3. Use fewer, but larger output capacitors, keep the

capacitors clustered, and use multiple layer traces with

heavy copper to keep the parasitic resistance low. Place

the output capacitors as close to the load as possible.

4. The inductor, output capacitor and the MOSFET should

be as close to each other as possible. This helps to reduce

the EMI radiated.

5. Place the switching MOSFET as close to the input

capacitors as possible. The MOSFET gate traces to the

IC must be as short, straight, and wide as possible. Use

copper filled polygons on the top and bottom layers for the

PHASE nodes.

6. Place the CBOOT as close as possible to the BOOT and

PHASE pins.

7. The feedback part of the system should be kept away

from the inductor and other noise sources, and be placed

close to the IC. Connect to the GND pin with a single

trace, and connect this local GND trace to the output

capacitor GND.

8. Minimize the leakage current paths on the OCSET/SD

pin and locate the resistor as close to the OCSET/SD pin

as possible because the internal current source is only

40μA.

9. In multilayer PCB, use one layer as ground plane and

have a control circuit ground (analog ground), to which all

signals are referenced. The goal is to localize the high

current path to a separate loop that does not interfere with

the more sensitive analog control function. These two

grounds must be connected together on the PC board

layout at a single point.

DS9212-05 March 2007

www.richtek.com

13

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