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RT9238

VRM8.5 PWM and Triple Linear Power System Controller

Richtek Technology 

Preliminary

RT9238

Functional Description

Operation

The RT9238 monitors and precisely controls 4 output

voltage levels (Refer to Figures 1, 2, and function

block). It is designed for microprocessor computer

applications with 3.3V, 5V, and 12V bias input from

an ATX power supply. The IC has one PWM and

three linear controllers. The PWM controller is

designed to regulate the microprocessor core voltage

(VOUT1). The PWM controller drives 2 MOSFETs (Q1

and Q2) in a synchronous-rectified buck converter

configuration and regulates the core voltage to a level

programmed by the 5-bit digital-to-analog converter

(DAC). The first linear controller (EA2) is designed to

provide the AGTL+ bus voltage (VOUT2) by driving a

MOSFET (Q3) pass element to regulate the output

voltage to a level of 1.2V. The remaining two linear

controllers (EA3 and EA4) supply the 1.5V advanced

graphics port (AGP) bus power (VOUT3) and the 1.8V

chipset core power (VOUT4).

Initialization

The RT9238 automatically initializes in ATX-based

systems upon receipt of input power. The Power-On

Reset (POR) function continually monitors the input

supply voltages. The POR monitors the bias voltage

(+12VIN) at the VCC pin, the 5V input voltage (+5VIN)

at the OCSET pin, and the 3.3V input voltage

(+3.3VIN) at the VAUX pin. The normal level on

OCSET is equal to +5VIN less a fixed voltage drop

(see over-current protection). The POR function

initiates soft-start operation after all supply voltages

exceed their POR thresholds.

Soft-Start

The 1.8V supply designed to power the chipset

(OUT4), cannot lag the ATX 3.3V by more than 2V, at

any time. To meet this special requirement, the linear

block controlling this output operates independently

of the chip’s power-on reset. Thus, DRIVE4 is driven

to raise the OUT4 voltage before the input supplies

reach their POR levels. As seen in Fig.3, at time T0

the power is turned on and the

input supplies ramp up. Immediately following, OUT4

is also ramped up, lagging the ATX 3.3V by about

1.8V. At time T1, the POR function initiates the SS24

soft-start sequence. Initially, the voltage on the SS24

pin rapidly increases to approximately 1V (this

minimizes the soft-start interval). Then, an internal

28µA current source charges an external capacitor

(CSS24) on the SS24 pin to about 4.5V. As the SS24

voltage increases, the EA2 error amplifier drives Q3

to provide a smooth transition to the final set voltage.

The OUT4 reference (clamped to SS24) increasing

past the intermediary level, established based on the

ATX 3.3V presence at the VAUX pin, brings the

output in regulation soon after T2.

As OUT2 increases past the 90% power-good level,

the second soft-start (SS13) is released. Between T2

and T3, the SS13 pin voltage ramps from 0V to the

valley of the oscillator’s triangle wave (at 1.25V).

Contingent upon OUT2 remaining above 1.08V, the

first PWM pulse on PHASE1 triggers the VTTPG pin

to go high. The oscillator’s triangular wave form is

compared to the clamped error amplifier output

voltage. As the SS13 pin voltage increases, the

pulse-width on the PHASE1 pin increases, bringing

the OUT1 output within regulation limits. Similarly, the

SS13 voltage clamps the reference voltage for OUT3,

enabling a controlled output voltage ramp-up. At time

T4, all output voltages are within power-good limits,

situation reported by the PGOOD pin going high.

The T2 to T3 time interval is dependent upon the

value of CSS13. The same capacitor is also

responsible for the ramp-up time of the OUT1 and

OUT3 voltages. If selecting a different capacitor then

recommended in the circuit application literature,

consider the effects the different value will have on

the ramp-up time and inrush currents of the OUT1

and OUT3 outputs.

DS9238-01 July 2001

www.richtek-ic.com.tw

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