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RT9238

VRM8.5 PWM and Triple Linear Power System Controller

Richtek Technology 

RT9238

Preliminary

elements. The voltage spikes can degrade efficiency,

radiate noise into the circuit, and lead to device over-

voltage stress. Careful component layout and printed

circuit design minimizes the voltage spikes in the

converter. Consider, as an example, the turn-off

transition of the upper MOSFET. Prior to turn-off, the

upper MOSFET was carrying the full load current.

During the turn-off, current stops flowing in the upper

MOSFET and is picked up by the lower MOSFET or

Schottky diode. Any inductance in the switched

current path generates a large voltage spike during

the switching interval. Careful component selection,

tight layout of the critical components, and short,

wide circuit traces minimize the magnitude of voltage

spikes.

There are two sets of critical components in a DC-DC

converter using an RT9238 controller. The switching

power components are the most critical because they

switch large amounts of energy, and as such, they

tend to generate equally large amounts of noise. The

critical small signal components are those connected

to sensitive nodes or those supplying critical bypass

current.

The power components and the controller IC should

be placed first. Locate the input capacitors, especially

the high-frequency ceramic de-coupling capacitors,

close to the power switches. Locate the output

inductor and output capacitors between the

MOSFETs and the load. Locate the PWM controller

close to the MOSFETs.

The critical small signal components include the

bypass capacitor for VCC and the soft-start capacitor,

CSS. Locate these components close to their

connecting pins on the control IC. Minimize any

leakage current paths from any SS node, since the

internal current source is only 28µA.

A multi-layer printed circuit board is recommended.

Fig.7 shows the connections of the critical

components in the converter. Note that the capacitors

CIN and COUT each could represent numerous

physical capacitors. Dedicate one solid layer for a

ground plane and make all critical

www.richtek-ic.com.tw

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component ground connections with vias to this layer.

Dedicate another solid layer as a power plane and

break this plane into smaller islands of common

voltage levels. The power plane should support the

input power and output power nodes. Use copper

filled polygons on the top and bottom circuit layers for

the PHASE node, but do not unnecessarily oversize

this particular island. Since the PHASE node is

subject to very high dV/dt voltages, the stray

capacitor formed between these island and the

surrounding circuitry will tend to couple switching

noise. Use the remaining printed circuit layers for

small signal wiring. The wiring traces from the control

IC to the MOSFET gate and source should be sized

to carry 2A peak currents.

+5VIN

LIN

CIN

+3.3VIN

Q3

VOU T2

+12V

CVCC

VCC GND

OCSET

DRIVE2

COUT2

UGATE

PHASE

CSS24,13

VOU T3

SS24

SS13

LGATE

RT9238

COUT3

Q4

DRIVE3 DRIVE4

PGND

COCSET

ROCSET

Q1

LOUT VOUT1

Q2

COUT1

CR1

VOU T4

Q5 COUT4

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT PLANE LAYER

VIA/THROUGH-HOLE CONNECTION TO GROUND PLANE

Fig.7 Layout Planning

PWM1 Controller Feedback Compensation

The PWM controller uses voltage-mode control for

output regulation.

An internal pole-zero

compensation scheme is used with an active

capacitor and a passive resistor shown in Fig.8. The

zero FZ1 is fixed at about 1kHz to compensate the

output ‘s LC pole FLC. The compensation is to

DS9238-01 July 2001

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