RTL8019AS Ver la hoja de datos (PDF) - Realtek Semiconductor

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RTL8019AS

Realtek Full-Duplex Ethernet Controller with Plug and Play Function (RealPNP)

Realtek Semiconductor 

SPECIFICATION

RTL8019AS

Mode 3: Loopback through the cable (LB1=1, LB0=1 in TCR)

The packets are transmitted via the MAU onto the network and RTL8009 receives all

incoming packets (not only the MAU-loopbacked Tx data) in the meantime.

NIC

Ref: 8390

SNI

83910

MAU

8392/RTL8005

CABLE

q Alignment of the Reception FIFO

The reception FIFO is an 8-byte ring structure. The first received byte is put at location zero.

When the location pointer goes to the end of the FIFO, it wraps to the beginning of the FIFO and

overwrites the previous data. At the end of the packet reception, the FIFO contents are in the

"order" (from the ring structure's view) as shown below.

(1) CRC enabled (CRC bit in TCR=0)

s 1-byte received packet data

s 4-byte CRC

s 1-byte lower byte count

s 1-byte upper byte count

s 1-byte upper byte count

(2) CRC disabled (CRC bit in TCR=1)

s 5-byte received packet data

s 1-byte lower byte count

s 1-byte upper byte count

s 1-byte upper byte count

6.6.2. To Implement Loopback Test

(1) To verify the integrity of data path

s set RCR=00h to accept physical packet

s set PAR0-5 to accept packet

s set DCR=40h (8-bit slot) or 43h (16-bit slot)

s set TCR=02h, 04h, 06h to do loopback test 1, 2, 3 respectively

s set CRC enabled (CRC=0 in TCR)

s clear ISR

s tx a packet and check ISR

s check FIFO after loopback

Note: Loopback mode 3 is sensitive to the network traffic, so the values of FIFO may be not

correct.

(2) To verify CRC logic

q Select a loopback mode (e.g. mode 2) to test

A. To test CRC generator

s set RCR=00h to accept physical packet

8019AS.doc

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2001-04-02

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