RTL8029AS Ver la hoja de datos (PDF) - Unspecified

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RTL8029AS

Realtek PCI Full-Duplex Ethernet Controller with built-in SRAM

Unspecified 

RTL8029AS Preliminary

CNTR1: CRC Error Tally Counter Register (0EH; Type=R in Page0)

CNTR2: Missed Packet Tally Counter Register (0FH; Type=R in Page0)

PAR0-5: Physical Address Registers (01H - 06H; Type=R/W in Page1)

These registers contain my Ethernet node address and are used to compare the

destination address of incoming packets for acceptation or rejection.

CURR: Current Page Register (07H; Type=R/W in Page1)

This register points to the page address of the first receive buffer page to be used for a

packet reception.

MAR0-7: Multicast Address Register (08H - 0FH; Type=R/W in Page1)

These registers provide filtering bits of multicast addresses hashed by the CRC logic.

5.1.2.2. RTL8029AS Defined Registers

Page 0 (PS1=0, PS0=0)

Two registers are defined to contain the RTL8029AS chip ID and Read Sequence Command is NO

LONGER supported in RTL8029AS.

No.

Name

0AH 8029ID0

0BH 8029ID1

Type

R

R

Bit7-0

50H (ASCII code of "P")

43H (ASCII code of "C")

Page 3(PS1=1, PS0=1)

Page3 Power Up Values before loading 9346 contents

No.

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0CH

0DH

0EH

0FH

Name

CR

9346CR

-

CONFIG0

-

CONFIG2

CONFIG3

-

-

HLTCLK

-

-

-

-

8029ASID0

8029ASID1

Type

R/W

R/W

R

R/W*

R/W*

W

R

R

Bit 7

0

0

-

*

-

1

0

1

Bit 6

0

0

-

*

*

1

0

0

Bit 5

1

-

-

0

*

1

1

0

Bit 4

0

-

-

0

*

1

0

0

Bit 3

0

*

-

-

-

1

1

0

Bit 2

0

*

*

-

0

1

0

0

Bit 1

0

*

0

*

0

1

0

0

Bit 0

1

*

0

*

-

1

1

0

LS009.0

17

1997.01.16

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