RTL8029AS Ver la hoja de datos (PDF) - Unspecified

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RTL8029AS

Realtek PCI Full-Duplex Ethernet Controller with built-in SRAM

Unspecified 

RTL8029AS Preliminary

1

PWRDN This bit, when set, puts RTL8029AS into power down mode.

RTL8029AS supports two kinds of power down modes, which is selected by the

contents of the HLTCLK register:

(1) mode 1: power down with clock running

(2) mode 2: power down with clock halted

In both power down modes, the RTL8029AS's serial network interface and

transceiver are turned off. All network activities are ignored.

All LED signals except LED_BNC are forced high. The LED_BNC is forced low

to disable the DC converter for coaxial transceiver.

In power down mode 2, the RTL8029AS stops its internal clock for minimal

power consumption. Registers except HLTCLK are typically not accessible in this

mode.

This bit's initial value comes from 9346 and can be modified if EEM1=EEM0=1

in 9346CR register.

0

-

Unused

HLTCLK: Halt Clock Register (09H; Type=W)

This is the only active one of Group1 registers when RTL8029AS is inactivated. Writing to this

register is invalid if RTL8029AS is not in power down mode. (i.e., If PWRDN bit in CONFIG3

register is zero.) The data written to this register determines the RTL8029AS's power down mode.

Data

52H (ASCII code of 'R')

48H (ASCII code of 'H')

Other values

Power Down Mode

Mode 1 - clock Running

Mode 2 - clock Halted

Ignored

8029ASID0,1: RTL8029AS ID = 8029H (0E,0FH; Type=R)

5.2. Group 2: PCI Configuration Space Registers

5.2.1. PCI Configuration Space Table

No. Name

00H VID

01H

02H DID

03H

04H Command

05H

06H Status

07H

08H RID

09H PIFR

0AH SCR

0BH BCR

0CH -

Type

R

R

R

R

R

W

R

W

R

R

R

R

R

R

Bit 7

VID7

VID15

DID7

DID15

0

-

0

-

0

0

0

0

0

0

Bit 6

VID6

VID14

DID6

DID14

0

-

0

-

0

0

0

0

0

0

Bit 5

VID5

VID13

DID5

DID13

0

-

0

-

0

0

0

0

0

0

Bit 4 Bit 3

VID4 VID3

VID12 VID11

DID4 DID3

DID12 DID11

0

0

-

-

0

0

-

-

0

0

0

0

0

0

0

0

0

0

0

0

Reserved

Bit 2

VID2

VID10

DID2

DID10

0

-

0

-

0

DST1

0

0

0

0

Bit 1

VID1

VID9

DID1

DID9

MEMEN

MEMEN

0

-

0

DST0

0

0

0

1

Bit 0

VID0

VID8

DID0

DID8

IOEN

IOEN

0

-

0

0

0

0

0

0

LS009.0

20

1997.01.16

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