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CD3206BB

9-bit latched/registered/pass-thru Futurebus+ transceiver

Philips Electronics 

Philips Semiconductors

9-bit latched/registered/pass-thru Futurebus+ transceiver

Product specification

FB2031

AC ELECTRICAL CHARACTERISTICS (Industrial)

B PORT LIMITS

SYMBOL

PARAMETER

TEST

CONDITION

Tamb = +25°C, VCC = 5V,

CD = 30pF, RU = 16.5Ω

MIN TYP MAX

Tamb = –40 to +85°C,

VCC = 5V±10%,

CD = 30pF, RU = 16.5Ω

MIN

MAX

UNIT

tPLH

tPHL

tPLH

tPHL

tPLH

tPHL

tPLH

tPHL

tPZH

tPZL

tTLH

tTHL

tSK(o)

tSK(p)

Propagation delay (thru mode)

An to Bn

Propagation delay (transparent latch)

An to Bn

Propagation delay

LCAB to Bn

Propagation delay

SEL0 or SEL1 to Bn

Enable/disable time

OEB0 or OEB1 to Bn

Output transition time, Bn Port

(1.3V to 1.8V)

Output to output skew for multiple

channels1

Pulse skew2

 tPHL – tPLH  MAX

Waveform 1, 2

1.0

3.0

5.0

1.0

2.7

4.0

1.5

1.5

Waveform 1, 2

1.0

3.2

5.0

1.0

3.1

4.2

1.5

1.5

Waveform 1, 2

2.0

4.0

5.5

1.5

4.0

5.5

1.5

1.5

Waveform 1, 2

2.0

3.5

5.5

1.5

2.3

4.5

2.0

1.0

Waveform 1, 2

1.5

3.0

5.0

1.2

2.4

4.5

1.0

1.0

Test Circuit and

1.0

Waveforms

0.6

2.0

0.9

3.0

0.6

Waveform 3

1.0

0.4

1.6

Waveform 2

0.3

1.0

5.7

4.5

ns

5.5

5.0

ns

6.5

6.0

ns

6.1

5.5

ns

5.7

5.5

ns

3.0

3.0

ns

1.6

ns

1.5

ns

NOTES:

1.  tPNactual – tPMactual  for any data input to output path compared to any other data input to output path where N and M are either LH or

HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.).

2. tSK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal

duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).

1995 May 25

10

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