SAA4951 Ver la hoja de datos (PDF) - Philips Electronics
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SAA4951 Datasheet PDF : 25 Pages
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Philips Semiconductors
Memory controller
Preliminary specification
SAA4951
Microcontroller interface
The SAA4951 is connected to a microcontroller via pins P0
to P7, ALE and WRD. This controller receives commands
from the I2C-bus and sets the registers of the
SAA4951 accordingly. Fig.4 shows the timing of these
signals. Address and data are transmitted sequentially on
the bus with the falling edge of ALE denoting a valid
address and the falling edge of WRD indicating valid data.
The individual registers, their address and their function
are listed in Table 1. Various start and stop registers are
9 bits wide, in this case the MSB is combined with other
MSBs or fine delay control bits in an extra register which
has to be addressed and loaded separately.
In order to load the proper values to the vertical write
enable registers in case of median filtering, information
about the current 100 Hz field is necessary. To obtain
these data, the microcontroller sends the address 80Hex
(READ mode) which puts the SAA4951 in output mode for
the next address / data cycle. For this one cycle the WRD
pin works as a RDN pin.
handbook, fuAllLpEagewidth
WRD
DATA
ADDRESS
DATA
ADDRESS
DATA
Fig.4 µP-interface timing.
Table 1 Internal registers.
ADDRESS
(HEX)
REGISTER
FUNCTION
Vertical pulses generated from the display clock
40
VDFLSTA
start of VDFL pulse (lower 8 of 9 bits)
41
VDFLSTO
end of VDFL pulse (lower 8 of 9 bits)
42
VWE2STA
start of vertical write enable (lower 8 of 9 bits)
43
VWE2STO
end of vertical write enable (lower 8 of 9 bits)
44
VRE2STA
start of vertical read enable (lower 8 of 9 bits)
45
VRE2STO
end of vertical write enable (lower 8 of 9 bits)
46
VDMSB
bit 0: MSB of VDFLSTA
bit 1: MSB of VDFLSTO
bit 2: MSB of VWE2STA
bit 3: MSB of VWE2STO
bit 4: MSB of VRE1STA
bit 5: MSB of VRE1STO
ADDRESS
MGH133
April 1994
8
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