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SAA4951

Memory controller

Philips Electronics 

Philips Semiconductors

Memory controller

Preliminary specification

SAA4951

ADDRESS

(HEX)

REGISTER

FUNCTION

Horizontal pulses generated from the display clock

48

BLNDSTA

start of horizontal blanking pulse (lower 8 of 9 bits)

49

BLNDSTO

end of horizontal blanking pulse (lower 8 of 9 bits)

4A

HWE2STA

start of horizontal write enable (lower 8 of 9 bits)

4B

HWE2STO

end of horizontal write enable (lower 8 of 9 bits)

4C

HRESTA

start of horizontal read enable (lower 8 of 9 bits)

4D

HRESTO

end of horizontal read enable (lower 8 of 9 bits)

4E

HDMSB

bit 0: MSB of BLNDSTA

bit 1: MSB of BLNDSTO

bit 2: MSB of HWE2STA

bit 3: MSB of HWE2STO

bit 4: MSB of HRESTA

bit 5: MSB of HRESTO

4F

HDDEL

bit 0: fine delay of BLND (LSB)

bit 1: fine delay of BLND (MSB)

bit 2: fine delay of HWE2 (LSB)

bit 3: fine delay of HWE2 (MSB)

bit 4: fine delay of HRE (LSB)

bit 5: fine delay of HRE (MSB)

Vertical pulses generated from the acquisition clock

50

VWE1STA

start of vertical write enable (lower 8 of 9 bits)

51

VWE1STO

end of vertical write enable (lower 8 of 9 bits)

52

VAMSB

bit 0: MSB of VWE1STA

bit 1: MSB of VWE1STO

Horizontal pulses generated from the acquisition clock

58

CLVSTA

start of CLV pulse

59

CLVSTO

end of CLV pulse

5A

HWE1STA

start of horizontal write enable (lower 8 of 9 bits)

5B

HWE1STO

end of horizontal write enable (lower 8 of 9 bits)

5C

HAMSBDEL

bit 0: MSB of HWE1STA

bit 1: MSB of HWE1STO

bit 2: fine delay of HWE1 (LSB)

bit 3: fine delay of HWE1 (MSB)

bit 4: memory configuration bit 2 (MC2): 0 = 1050/60; 1 = 1070/2970

bit 5: WEXT (external WE)

bit 6: SFR (select field recognition)

April 1994

9

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