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SAA7112

Decoder with High-Performance Scaler (HPS) for Image Port (PELICAN)

Philips Electronics 

Philips Semiconductors

Decoder with High-Performance Scaler

(HPS) for Image Port (PELICAN)

Preliminary specification

SAA7112

handbook, full pagewidth

HRWNF

HACNSD

HADP

HDSNSC

HCST

HPD7

to

HPD0

chroma of 16-bit

input mode

a

data, clock, H, V, FID

and qualifier from

scaler input

selector

HOST PORT PIN MAPPING

I2C-BUS

chroma of 16-bit output mode

PROG. PORT CONTROL

PROGRAMMING

REGISTER

ARRAY

SLEEP MODE REGISTER

from

event

controller

A/B

REGISTER

MUX

CLOCK MULTIPLEXER

INCLUDING

TCB

INPUT

FIR-FILTER

LUMINANCE

PRESCALING

LUMINANCE

4:2:2

LINE

VERTICAL

SCALING

PROCESSOR

HORIZONTAL

PHASE SCALING

LUMINANCE

b

ACQUISITION

BCS

FIFO

CONTROL

FIR FILTER

PRESCALING

CHROMINANCE CHROMINANCE

CONTROL

BUFFER

LINE MEMORY

1H * 16 BIT

HORIZONTAL

PHASE SCALING

CHROMINANCE

EVENT

CONTROLLER

data, clock and

reference signals

from text input

selector

c

OUTPUT

ACQUISITION

CONTROL

YUV

OUTPUT

FORMAT

GENERAL

PURPOSE

TEXTSLICER

TXT

INTERFACE

VIDEO

FIFO

32 × 32

FIFO

CONTROL

32

TO

8 (16)

MUX

FIFO

CONTROL

TEXT

FIFO

16 × 32

32

TO

8 (16)

MUX

VIDEO / TEXT

ARBITER

LPB

PROG

IMAGE

PORT

PIN

MAPPING

FF

IP

OUT

LPB

VIDEO

OUT

MGE860

IPD7

to

IPD0

IRH

IRV

IDQE

ICRQF

ITRDY

ICLK

ITRI

1996 Jun 20

Fig.2 Block diagram (continued from Fig.1).

5

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