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SC4603

Very Low Input, MHz Operation, High Efficiency Synchronous Buck

Semtech Corporation 

SC4603

POWER MANAGEMENT

Pin Configuration

Top View

(10 Pin MSOP)

Ordering Information

Part Number(1)

SC4603IMSTRT(2)

Device

MSOP-10

Notes:

(1) Only available in tape and reel packaging. A reel

contains 2500 devices.

(2) Lead free product. This product is fully WEEE and

RoHS compliant.

Pin Descriptions

VCC: Positive supply rail for the IC. Bypass this pin to

GND with a 0.1 to 4.7µF low ESL/ESR ceramic capaci-

tor.

GND: All voltages are measured with respect to this pin.

All bypass and timing capacitors connected to GND should

have leads as short and direct as possible.

FS: An external resistor connected with FS pin sets the

clock frequency.

SYNC/SLEEP: The oscillator frequency of SC4603 is

set by FS when SYNC/SLEEP is pulled and held above

2V. Its synchronous mode operation is activated as the

SYNC/SLEEP is driven by an external clock. The oscilla-

tor and PWM are designed to provide practical operation

to 1MHz when synchronized. Sleep mode is invoked if

SYNC/SLEEP is pulled and held below 0.8V which can be

accomplished by an external gate or transistor. The

Sleepmode supply current is 10µA typical.

VSENSE: This pin is the inverting input of the voltage

amplifier and serves as the output voltage feedback point

for the Buck converter. It senses the output voltage through

an external divider.

PHASE, ISET: PHASE input is connected to the junction

between the two external power MOSFET transistors. The

voltage drop across the upper P-channel device is moni-

tored by PHASE and ISET during PFET conduction and

forms the current limit comparator and logic that sets

the PWM latch and terminates the PFET output pulse

once excessive voltage drop across the PFET is detected.

The controller stops switching and goes through a soft

start sequence once the converter output voltage drops

below 70% its nominal voltage. This prevents excess

power dissipation in the PMOSFET during a short circuit.

The current limit threshold is set by the external resistor

between VCC and ISET. The internal 50µA current source

has a positive temperature coefficient that can compen-

sate PMOSFET Rdson variation due to its junction tem-

perature change.

PDRV, NDRV: The PWM circuitry provides complemen-

tary drive signals to the output stages. The Cross con-

duction of the external MOSFETs is prevented by moni-

toring the voltage on the P-channel and N-channel driver

pins in conjunction with a time delay optimized for FET

turn-off characteristics.

COMP: This is the output of the voltage amplifier. The

voltage at this output is connected to the inverting input

of the PWM comparator. A lead-lag network around the

voltage amplifier compensates for the two pole LC filter

characteristic inherent to voltage mode control and is

required in order to optimize the dynamic performance

of the voltage mode control loop.

 2008 Semtech Corp.

5

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