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SC4603

Very Low Input, MHz Operation, High Efficiency Synchronous Buck

Semtech Corporation 

POWER MANAGEMENT

Block Diagram

SC4603

Applications Information

Enable

Pulling and holding the SYNC/SLEEP pin below 0.8V ini-

tializes the SLEEP mode of the SC4603 with its typical

SLEEP mode supply current of 10uA. During the SLEEP

mode, the high side and low side MOSFETs are turned

off and the internal soft start voltage is held low.

fS

=

126 •108

RT

An external clock connected to the SYNC/SLEEP acti-

vates its synchronous mode and the frequency of the

clock can be up to 1MHz.

Oscillator

UVLO

The oscillator uses an external resistor to set the oscilla-

tion frequency when the SYNC/SLEEP pin is pulled and

held above 2V. The ramp waveform is a triangle at the

PWM frequency with a peak voltage of 1.25V and a val-

ley voltage of 0.25V. A 100% maximum duty cycle allows

the SC4603 to operate as a low dropout regulator in the

event of a low battery condition. The resistor tolerance

adds to the accuracy of the oscillator frequency. The ex-

ternal resistor connected to the FS pin, as shown below

determines the approximate operating frequency:

When the SYNC/SLEEP pin is pulled and held above 2V,

the voltage on the VCC pin determines the operation of

the SC4603. As VCC increases during start up, the UVLO

block senses V and keeps the high side and low side

CC

MOSFETs off and the internal soft start voltage low until

VCC reaches 2.25V. If no faults are present, the SC4603

will initiate a soft start when VCC exceeds 2.25V. A

hysteresis (100mV) in the UVLO comparator provides

noise immunity during its start up.

 2008 Semtech Corp.

7

www.semtech.com

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