SCC2681T Ver la hoja de datos (PDF) - Philips Electronics
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SCC2681T Datasheet PDF : 15 Pages
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Philips Semiconductors
Dual asynchronous receiver/transmitter (DUART)
PIN CONFIGURATION
Product data
SCC2681T
IP2 40
IP6 41
IP5 42
IP4 43
VCC 44
n.c. 1
A0 2
IP3 3
A1 4
IP1 5
A2 6
SCC2681TC1A44
28 D0
27 D2
26 D4
25 D6
24 INTRN
23 n.c.
22 GND
21 D7
20 D5
19 D3
18 D1
SD00737
Figure 2. Pin configuration
PIN DESCRIPTION
MNEMONIC
PIN
D0–D7
21, 25, 20,
26, 19, 27,
18, 28
CEN
39
WRN
RDN
A0–A3
RESET
9
10
2, 4, 6, 7
38
INTRN
24
X1/CLK
36
X2
37
RxDA
35
RxDB
11
TYPE
NAME AND FUNCTION
I/O Data Bus: Bidirectional three-state data bus used to transfer commands, data and status between the
DUART and the CPU. D0 is the least significant bit.
I Chip Enable: Active LOW input signal. When LOW, data transfers between the CPU and the DUART
are enabled on D0–D7 as controlled by the WRN, RDN, and A0–A3 inputs. When CEN is HIGH, the
DUART places the D0–D7 lines in the three-state condition.
I Write Strobe: When LOW and CEN is also LOW, the contents of the data bus is loaded into the
addressed register. The transfer occurs on the rising edge of the signal.
I Read Strobe: When low and CEN is also LOW, causes the contents of the addressed register to be
presented on the data bus. The read cycle begins on the falling edge of RDN.
I Address Inputs: Select the DUART internal registers and ports for read/write operations.
I Reset: A HIGH level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0–OP7 in the
HIGH state, stops the counter/timer, and puts channels A and B in the inactive state, with the TxDA and
TxDB outputs in the mark (HIGH) state. Clears Test modes, sets MR pointer to MR1.
O Interrupt Request: Active-LOW, open-drain output which signals the CPU that one or more of the eight
maskable interrupting conditions are true.
I Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency
(nominally 3.6864 MHz) must be supplied at all times. For crystal connections see Figure 7, Clock
Timing.
I Crystal 2: Crystal connection. See Figure 7. If a crystal is not used it is best to keep this pin not
connected.
It must not be grounded.
I Channel A Receiver Serial Data Input: The least significant bit is received first. ‘Mark’ is HIGH, ‘space’
is LOW.
I Channel B Receiver Serial Data Input: The least significant bit is received first. ‘Mark’ is HIGH, ‘space’
is LOW.
2004 Apr 06
4
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