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SCC2681T

Dual asynchronous receiver/transmitter (DUART)

Philips Electronics 

Philips Semiconductors

Dual asynchronous receiver/transmitter (DUART)

Product data

SCC2681T

4. Test conditions for outputs: CL = 150 pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50 pF, RL = 2.7 kΩ to VCC.

5. For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle

and the signal negated first terminates the cycle.

6. If CEN is used as the ‘strobing’ input, the parameter defines the minimum HIGH times between one CEN and the next. The RDN signal must

be negated for tEHEL to guarantee that any status register changes are valid. As a consequence, this minimum time must be met for the

RDN input even if the CEN is used as the strobing signal for bus operations.

7. Consecutive write operations to the same command register require at least three edges of the X1 clock between writes.

8. Minimum frequencies are not tested but are guaranteed by design.

RESET

tRES

Figure 3. Reset Timing

SD00028

A0–A3

CEN

(READ)

tAVEL

RDN

D0–D7

(READ)

tRLDA

FLOAT

tELAX

tRLRH

tRLDV

INVALID

tEHEL

tRHDF

tRHDI

VALID

CEN

(WRITE)

WRN

D0–D7

(WRITE)

tWLWH

tDVWH

VALID

tEHEL

tWHDI

Figure 4. Bus Timing

FLOAT

SD00100

2004 Apr 06

9

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