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CD128410QCE

IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports

Intel 

CD1284 — IEEE 1284-Compatible Parallel Interface Controller

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Functional Block Diagram ................................................................................... 11

CD1284 Sample System Block Diagram ............................................................ 14

CD1284 Functional Block Diagram ..................................................................... 32

Internal Address Generation ............................................................................... 32

Control Signal Generation................................................................................... 38

CD1284 Daisy-Chain Connections ..................................................................... 42

Interrupt Generation Logic .................................................................................. 45

FIFO Timer Processing ....................................................................................... 53

CD1284 Receive Character Processing ............................................................. 64

CD1284 Transmit Character Processing ............................................................ 70

FIFO Data Path Functional Diagram — Receive ................................................ 78

FIFO Data Path Functional Diagram — Transmit ............................................... 80

Cable Connection................................................................................................ 85

External Buffer Control........................................................................................ 86

Intel‚ 80x86 Family Interface ............................................................................... 87

Motorola‚ 68020 Interface ................................................................................... 88

National Semiconductor‚ 32000 Interface ........................................................... 89

Flow Diagram of CD1284 Master Initialization Sequence................................... 92

Polling Flow Chart ............................................................................................. 100

Reset Timing ..................................................................................................... 158

Clock Timing ..................................................................................................... 159

Asynchronous Read Cycle Timing .................................................................... 159

Asynchronous Write Cycle Timing .................................................................... 160

Asynchronous Service Acknowledge Cycle Timing .......................................... 161

Asynchronous DMA Read Cycle Timing ........................................................... 162

Asynchronous DMA Read Cycle Timing (Two Back-to-Back DMA Reads) ...... 162

Asynchronous DMA Write Cycle Timing ........................................................... 163

Asynchronous DMA Write Cycle Timing (Two Back-to-Back DMA Writes)....... 163

Synchronous Read Cycle Timing...................................................................... 165

Synchronous Write Cycle Timing ...................................................................... 166

Synchronous Service Acknowledge Cycle Timing ............................................ 167

Synchronous DMA Write Cycle Timing

(Two Back-to-Back 3-Cycle DMA Writes) ......................................................... 168

Synchronous DMA Read Cycle Timing

(Two Back-to-Back 3-Cycle DMA Reads) ......................................................... 168

UART to RS232 and IR Port Interface Motherboard Example Schematic ........ 172

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