SI2401 Ver la hoja de datos (PDF) - Silicon Laboratories

Número de pieza

componentes Descripción

Lista de partido

SI2401

V.22BIS ISOMODEM® WITH LOW-COST DAA

Silicon Laboratories 

Si2401/Si3008

echoed by the Si2401 is an “N” (no carrier).

Successful completion of a turnaround procedure in

master or slave mode automatically updates

S07[4] (V23T) and S07[5] (V23R) to indicate the new

status of the V.23 connection.

To avoid using the INT pin, the host may also be notified

of the INT condition by using 9-bit data mode. Setting

S15[0] (NBE) = 1 and S0C[3] (9BF) = 0b configures the

ninth bit on the Si2401 TXD path to function exactly as

the INT pin has been described.

4.7. V.42 HDLC Mode

The Si2401 supports V.42 through hardware HDLC

framing in all modem data modes. Frame packing and

unpacking including opening and closing flag generation

and detection, CRC computation and checking, zero

insertion and deletion, and modem data transmission

and reception are all performed by the Si2401. V.42

error correction and V.42bis data compression must be

performed by the host.

The digital link interface in this mode uses the same

UART interface (8-bit data and 9-bit data formats) as in

the asynchronous modes, and the ninth data bit may be

used as an escape by setting S15[0] (NBE) = 1. When

using HDLC in 9-bit data mode, if the ninth bit is not

used as an escape, it is ignored.

To use the HDLC feature on the Si2401, the host must

enable HDLC operation by setting S13[1] (HDEN) = 1.

The host may initiate the call or answer the call using

either the “ATDT#”, the “ATA” command or the auto-

answer mode. (The auto-answer mode is implemented

by setting register S00 (NR) to a non-zero value.) When

the call is connected, a “c”, “d”, or “v” is echoed to the

host controller. The host may now send/receive data

across the UART using either the 8-bit or 9-bit data

formats with flow control.

At this point, the Si2401 begins framing data into the

HDLC format. On the transmit side, if no data is

available from the host, the HDLC flag pattern is sent

repeatedly. When data is available, the Si2401

computes the CRC code throughout the frame, and the

data is sent with the HDLC zero-bit insertion algorithm.

HDLC flow control operates in a manner similar to

normal asynchronous flow control across the UART and

is shown in Figure 4. To operate flow control (using the

CTS pin to indicate when the Si2401 is ready to accept

a character), a DTE rate higher than the line rate should

be selected. The method of transmitting HDLC frames

is as follows:

1. After the call is connected, the host should begin

sending the frame data to the Si2401 using the CTS

flow control to ensure data synchronicity.

2. When the frame is complete, the host should simply

stop sending data to the Si2401. Since the Si2401

does not yet recognize the end-of-frame, it expects

an extra byte and assert CTS as shown in Figure 4A.

If CTS is used to cause a host interrupt, this final

interrupt should be ignored by the host.

3. When the Si2401 is ready to send the next byte, if it

has not yet received any data from the host, it

recognizes this as an end-of-frame, raise CTS,

calculates the final CRC code, transmits the code,

and begins transmitting stop flags.

4. After transmitting the first stop flag, the Si2401

lowers CTS, indicating that it is ready to receive the

next frame from the host. At this point, the process

repeats as in Step 1.

The method of receiving HDLC frames is as follows:

1. After the call is connected, the Si2401 searches for

flag data. Then, once the first non-flag word is

detected, the CRC is continuously computed, and

the data is sent across the UART (8-bit data or 9-bit

data mode) to the host after removing the HDLC

zero-bit insertion. The DTE rate of the host must be

at least as high as that of data transmission. HDLC

mode only works with 8-bit data words; the ninth bit

is used only for escape on TXD and end-of-frame

received (EOFR) on RXD.

2. When the Si2401 detects the stop flag, it sends the

last data word in the frame as well as the two CRC

bytes and determines if the CRC checksum

matches. Thus, the last two bytes are not frame data

but are the CRC bytes, which can be discarded by

the host. If the checksum matches, the Si2401

echoes “G” (good). If the checksum does not match,

the Si2401 echoes “e” (error). Additionally, if the

Si2401 detects an abort (seven or more contiguous

ones), it echoes an “A”.

When the “G”, “e”, or “A” (referred to as a frame

result word) is sent, the Si2401 raises the EOFR

(end of frame receive) pin (see Figure 4B). The

GPIO1 pin must be configured as EOFR by setting

SE4[3] (GPE) = 1. In addition to using the EOFR pin

to indicate that the byte is a frame result word, if in 9-

bit data mode (set S15[0] (NBE) = 1), the ninth bit is

raised if the byte is a frame result word. To program

this mode, set S0C[3] (9BF) = 1 and

SE0[3] (ND) = 1.

3. When the next frame of data is detected, EOFR is

lowered, and the process repeats at Step 1.

Rev. 1.1

17

Share Link: