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SI2401

V.22BIS ISOMODEM® WITH LOW-COST DAA

Silicon Laboratories 

Si2401/Si3008

To summarize, when receiving HDLC frames, the host

begins receiving data asynchronously from the Si2401.

When each byte is received, the host should check the

EOFR pin (or the ninth bit). If the EOFR pin (or the ninth

bit) is low, the data is valid frame data. If the EOFR pin

(or the ninth bit) is high, the data is a frame result word.

4.8. Fast Connect

In modem applications that require fast connection

times, it is possible to reduce the length of the

handshake.

Additional modem handshaking control can be adjusted

through the registers shown in Table 11. These registers

are most useful if the user has control of both the

originating and answering modems.

When the fast connect settings are used, there may be

unintended data received initially.The host must tolerate

these bytes.

4.9. Clock Generation Subsystem

The Si2401 contains an on-chip clock generator. Using

a single master clock input, the Si2401 can generate all

modem sample rates necessary to support V.22bis,

V.22/Bell212A, and V.21/Bell103 standards and a

9.6 kHz rate for audio playback. Either a 27 MHz or

4.9152 MHz clock on XTALI or a 4.9152 MHz crystal

across XTALI and XTALO form the master clock for the

Si2401. This clock source is sent to an internal phase-

locked loop (PLL) that generates all necessary internal

system clocks. The PLL has a settling time of ~1 ms.

Data on RXD should not be sent to the device prior to

settling of the PLL. By default, the Si2401 assumes a

4.9152 MHz clock input. If a 27 MHz clock on XTALI is

used, a pulldown resistor <10 kΩ must be placed

between GPIO4 (Si2401, pin 11) and GND.

Host begins frame N

Host finished sending frame N Host begins frame N + 1

TXD

Start

Si2401 ready for byte 1 of frame N

CTS

Note: Figure not to scale.

Frame N

(CTS used as normal flow control.)

Stop

Si2401 detects end of frame N.

Start

Si2401 ready for byte 1

of frame N + 1.

A. Frame Transmit

Frame N + 1

RXD

Start

Receive Data Stop Start CRC Byte 1 Stop

Start

CRC Byte 2 Stop Start Frame Result Word Stop

EOFR

(or bit 9)

B. Frame Receive

Figure 4. HDLC Timing

18

Rev. 1.1

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