CS8415A-IS Ver la hoja de datos (PDF) - Cirrus Logic
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CS8415A-IS Datasheet PDF : 42 Pages
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CS8415A
8.4 Serial Audio Output Port Data Format (06h) .................................................................... 21
8.5 Interrupt 1 Status (07h) (Read Only) ................................................................................ 22
8.6 Interrupt 2 Status (08h) (Read Only) ................................................................................ 23
8.7 Interrupt 1 Mask (09h) ...................................................................................................... 23
8.8 Interrupt 1 Mode MSB (0Ah) and Interrupt 1 Mode LSB(0Bh).......................................... 23
8.9 Interrupt 2 Mask (0Ch)...................................................................................................... 24
8.10 Interrupt 2 Mode MSB (0Dh) and Interrupt 2 Mode LSB(0Eh) ....................................... 24
8.11 Receiver Channel Status (0Fh) (Read Only) .................................................................. 24
8.12 Receiver Error (10h) (Read Only)................................................................................... 25
8.13 Receiver Error Mask (11h) ............................................................................................. 26
8.14 Channel Status Data Buffer Control (12h) ...................................................................... 26
8.15 User Data Buffer Control (13h) ....................................................................................... 27
8.16 Q-Channel Subcode Bytes 0 to 9 (14h - 1Dh) (Read Only) ........................................... 27
8.17 OMCK/RMCK Ratio (1Eh) (Read Only).......................................................................... 27
8.18 C-bit or U-bit Data Buffer (20h - 37h) ............................................................................. 27
8.19 CS8415A I.D. and Version Register (7Fh) (Read Only) ................................................. 27
9. PIN DESCRIPTION - SOFTWARE MODE ............................................................................. 28
10. HARDWARE MODE ............................................................................................................. 30
10.1 Serial Audio Port Formats ............................................................................................. 30
11. PIN DESCRIPTION - HARDWARE MODE .......................................................................... 31
12. APPLICATIONS .................................................................................................................. 33
12.1 Reset, Power Down and Start-up .................................................................................. 33
12.2 ID Code and Revision Code .......................................................................................... 33
12.3 Power Supply, Grounding, and PCB layout ................................................................... 33
13. PACKAGE DIMENSIONS ................................................................................................... 34
14. APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 RECEIVER COMPONENTS ............. 36
14.1 AES3 Receiver External Components ........................................................................... 36
14.2 Isolating Transformer Requirements ............................................................................. 36
15. APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT ........... 38
15.1 AES3 Channel Status (C) Bit Management ................................................................... 38
15.2 Accessing the E buffer ................................................................................................... 38
15.2.1 Reserving the first 5 bytes in the E buffer ......................................................... 38
15.2.2 Serial Copy Management System (SCMS) ....................................................... 39
15.2.3 Channel Status Data E Buffer Access .............................................................. 39
15.2.3.1 One Byte mode ................................................................................. 39
15.2.3.2 Two Byte mode ................................................................................. 39
15.3 AES3 User (U) Bit Management .................................................................................... 39
16. APPENDIX C: PLL FILTER .................................................................................................. 40
16.1 General .......................................................................................................................... 40
16.2 External Filter Components ........................................................................................... 41
16.2.1 General ............................................................................................................. 41
16.2.2 Capacitor Selection ........................................................................................... 41
16.2.3 Circuit Board Layout ......................................................................................... 41
16.2.4 Component Value Selection ............................................................................. 42
16.2.5 Jitter Attenuation ............................................................................................... 42
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