CS8415A-IS Ver la hoja de datos (PDF) - Cirrus Logic
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CS8415A-IS Datasheet PDF : 42 Pages
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CS8415A
DC ELECTRICAL CHARACTERISTICS (AGND = DGND = 0 V; all voltages with respect to 0 V.)
Parameters
Symbol Min Typ Max Units
Power-down Mode (Note 3)
Supply Current in power down
VA+
VL+ = 3 V
VL+ = 5 V
-
20
-
µA
-
60
-
µA
-
60
-
µA
Normal Operation (Note 4)
Supply Current at 48 kHz frame rate
VA+
VL+ = 3 V
VL+ = 5 V
-
6.3
-
mA
-
30.1
-
mA
-
46.5
-
mA
Supply Current at 96 kHz frame rate
VA+
VL+ = 3 V
VL+ = 5 V
-
6.6
-
mA
-
44.8
-
mA
-
76.6
-
mA
Notes: 3. Power Down Mode is defined as RST = LO with all clocks and data lines held static.
4. Normal operation is defined as RST = HI.
DIGITAL INPUT CHARACTERISTICS
Parameters
Input Leakage Current
Differential Input Voltage, RXP0 to RXN0
Symbol Min Typ Max Units
Iin
-
±1
±10
µA
VTH
-
200
-
mV
DIGITAL INTERFACE SPECIFICATIONS (AGND = DGND = 0 V; all voltages with respect to 0 V.)
Parameters
High-Level Output Voltage (IOH = -3.2 mA)
Low-Level Output Voltage (IOH = 3.2 mA)
High-Level Input Voltage, except RXn
Low-Level Input Voltage, except RXn
(Note 5)
Symbol
VOH
VOL
VIH
VIL
Min
Max
(VL+) - 1.0
-
-
0.4
2.0 (VL+) + 0.3
-0.3
0.4/0.8
Units
V
V
V
V
Notes: 5. At 5V mode, VIL = 0.8V (Max), at 3V mode, VIL =0.4V (Max).
SWITCHING CHARACTERISTICS
(Inputs: Logic 0 = 0V, Logic 1 = VL+; CL = 20 pF)
Parameter
Symbol Min
RST pin Low Pulse Width
200
PLL Clock Recovery Sample Rate Range
8.0
RMCK output jitter
-
RMCK output duty cycle
(Note 6)
40
Notes: 6. Cycle-to-cycle using 32-96kHz external PLL filter components.
Typ Max Units
-
-
µs
-
108.0 kHz
200
- ps RMS
50
60
%
6
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