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CS8405A-IS

96 kHz Digital Audio Interface Transmitter

Cirrus Logic 

CS8405A

5. AES3 TRANSMITTER

The CS8405A includes an AES3 digital audio

transmitter. A comprehensive buffering scheme

provides write access to the channel status and

user data. This buffering scheme is described in

“Appendix B: Channel Status and User Data Buffer

Management” on page 35.

The AES3 transmitter encodes and transmits au-

dio and digital data according to the AES3,

IEC60958 (S/PDIF), and EIAJ CP-1201 interface

standards. Audio and control data are multiplexed

together and bi-phase mark encoded. The result-

ing bit stream is driven to an output connector ei-

ther directly or through a transformer. The

transmitter is clocked from the clock input pin,

OM-K. If OMCK is asynchronous to the data

source, an interrupt bit (TSLIP) is provided that will

go high every time a data sample is dropped or re-

peated. Be aware that the pattern of slips does not

have hysteresis and so the occurrence of the inter-

rupt condition is not deterministic.

The channel status (C) and user (U) bits in the

transmitted data stream are taken from storage ar-

eas within the CS8405A. The user can manually

access the internal storage or configure the

CS8405A to run in one of several automatic

modes. “Appendix B: Channel Status and User

Data Buffer Management” on page 35 provides de-

tailed descriptions of each automatic mode and de-

scribes methods of manually accessing the

storage areas. The transmitted user bit data can

optionally be input through the U pin, under the

control of a control port register bit. Figure 7 shows

the timing requirements for inputting U data

through the U pin.

5.1 Transmitted Frame and Channel

Status Boundary Timing

The TCBL pin is used to control or indicate the start

of transmitted channel status block boundaries and

may be an input or an output.

In some applications, it may be necessary to con-

trol the precise timing of the transmitted AES3

frame boundaries. This may be achieved in two

ways:

a) With TCBL set to input, driving TCBL high for >3

OMCK clocks will cause a frame start, as well as a

new channel status block start.

b) If the serial audio input port is in slave mode and

TCBL is set to output, the start of the A channel

sub-frame will be aligned with the leading edge of

ILRCK.

5.2 TXN and TXP Drivers

The line drivers are low skew, low impedance, dif-

ferential outputs capable of driving cables directly.

Both drivers are set to ground during reset (RST =

low), when no AES3 transmit clock is provided,

and optionally under the control of a register bit.

The CS8405A also allows immediate muting of the

AES3 transmitter audio data through a control reg-

ister bit.

External components are used to terminate and

isolate the external cable from the CS8405A.

These components are detailed in “Appendix A:

External AES3/SPDIF/IEC60958 Transmitter and

Receiver Components” on page 34.

5.3 Mono Mode Operation

An AES3 stream may be used in more than one

way to transmit 96 kHz sample rate data. One

method is to double the frame rate of the current

format. This results in a stereo signal with a sample

rate of 96 kHz, carried over a single twisted pair

cable. An alternate method is implemented using

the two sub-frames in a 48 kHz frame rate AES3

signal to carry consecutive samples of a mono sig-

nal, resulting in a 96 kHz sample rate stream. This

allows older equipment, whose AES3 transmitters

and receivers are not rated for 96 kHz frame rate

operation, to handle 96 kHz sample rate informa-

tion. In this “mono mode”, two AES3 cables are

needed for stereo data transfer. The CS8405A of-

fers mono mode operation. The CS8405A is set to

mono mode by the MMT control bit.

In mono mode, the input port will run at the audio

sample rate (Fs), while the AES3 transmitter frame

rate will be at Fs/2. Consecutive left or right chan-

nel serial audio data samples may be selected for

transmission on the A and B sub-frames, and the

channel status block transmitted is also selectable.

Using mono mode is only necessary if the incom-

ing audio sample rate is already at 96 kHz and

contains both left and right audio data words. The

“mono mode” AES3 output stream may also be

achieved by keeping the CS8405A in normal

DS469F2

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