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CS8405A-IS

96 kHz Digital Audio Interface Transmitter

Cirrus Logic 

CS8405A

6. CONTROL PORT DESCRIPTION AND

TIMING

The control port is used to access the registers, al-

lowing the CS8405A to be configured for the de-

sired operational modes and formats. In addition,

Channel Status and User data may be read and

written through the control port. The operation of

the control port may be completely asynchronous

with respect to the audio sample rate.

The control port has two modes: SPI and I²C, with

the CS8405A acting as a slave device. SPI mode

is selected if there is a high to low transition on the

AD0/CS pin after the RST pin has been brought

high. I²C mode is selected by connecting the

AD0/CS pin to VL+ or DGND, thereby permanently

selecting the desired AD0 bit address state.

6.1 SPI Mode

In SPI mode, CS is the CS8405A chip select sig-

nal, CCLK is the control port bit clock (input into the

CS8405A from the microcontroller); CDIN is the in-

put data line from the microcontroller; and CDOUT

is the output data line to the microcontroller. Data

is clocked in on the rising edge of CCLK and out on

the falling edge.

Figure 8 shows the operation of the control port in

SPI mode. To write to a register, bring CS low. The

first seven bits on CDIN form the chip address and

must be 0010000. The eighth bit is a read/write in-

dicator (R/W), which should be low to write. The

next eight bits form the Memory Address Pointer

(MAP), which is set to the address of the register

that is to be updated. The next eight bits are the

data which will be placed into the register designat-

ed by the MAP. During writes, the CDOUT output

stays in the Hi-Z state. It may be externally pulled

high or low with a 47 kΩ resistor, if desired.

There is a MAP auto increment capability, enabled

by the INCR bit in the MAP register. If INCR is a

zero, the MAP will stay constant for successive

read or writes. If INCR is set to a 1, then the MAP

will auto increment after each byte is read or

written, allowing block reads or writes of

successive registers.

To read a register, the MAP has to be set to the

correct address by executing a partial write cycle

which finishes (CS high) immediately after the

MAP byte. The MAP auto increment bit (INCR)

may be set or not, as desired. To begin a read,

bring CS low, send out the chip address and set

the read/write bit (R/W) high. The next falling edge

of CCLK will clock out the MSB of the addressed

register (CDOUT will leave the high impedance

state). If the MAP auto increment bit is set to 1, the

data for successive registers will appear

consecutively.

6.2 I²C Mode

In I²C Mode, SDA is a bidirectional data line. Data

is clocked into and out of the part by the clock,

SCL, with the clock to data relationship as shown

in Figure 9. There is no CS pin. Each individual

CS8405A is given a unique address. Pins AD0,

AD1, and AD2 form the three least significant bits

CS

CCLK

C D IN

C H IP

ADDRESS

0010000

M AP

DATA

R/W

MSB

LSB

b y te 1

b y te n

C H IP

ADDRESS

0010000 R/W

CDOUT

High Impedance

MSB

LSB MSB

LSB

MAP = Memory Address Pointer, 8 bits, MSB first

Figure 8. Control Port Timing in SPI Mode

DS469F2

15

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