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CS8413
Cirrus-Logic
Cirrus Logic Cirrus-Logic
CS8413 Datasheet PDF : 38 Pages
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CS8413 CS8414
contained at the end of the Status and IEnable Reg-
isters section.
CS8414 DESCRIPTION
The CS8414 does not need a microprocessor to
handle the non-audio data (although a micro may
be used with the C and U serial ports). Instead, ded-
icated pins are available for the most important
channel status bits. The CS8414 is a monolithic
CMOS circuit that receives and decodes digital au-
dio data which was encoded according to the digital
audio interface standards. It contains an RS422 line
receiver and clock and data recovery utilizing an
on-chip phase-locked loop. The audio data is out-
put through a configurable serial port that supports
14 formats. The channel status and user data have
their own serial pins and the validity flag is OR’ed
with the ERF flag to provide a single pin, VERF,
indicating that the audio output may not be valid.
This pin may be used by interpolation filters that
provide error correction. A block diagram of the
CS8414 is illustrated in Figure 16.
The line receiver and jitter performance are de-
scribed in the sections directly preceding the
CS8413 sections in the beginning of this data sheet.
Audio Serial Port
The audio serial port is used primarily to output au-
dio data and consists of three pins: SCK, FSYNC,
and SDATA. These pins are configured via four
control pins: M0, M1, M2, and M3. M3 selects be-
tween eight normal serial formats (M3 = 0), and six
special formats (M3 = 1).
VA+
22
RXP 9
RXN
10
FILT AGND MCK
20
21
19
Clock & Data
Recovery
Bi-phase
Decoder
and
Frame
Sync
Timing
De-Multiplexer
7
VD+
8
DGND
CS12/ 13
FCK
Parity
Check
Frequency
Comparator
3
Error
Encoder
3
CRC
check
Channel
Status
Latch
SEL 16
6
6
Multiplexer
6 5 4 3 2 27
C0/ Ca/ Cb/ Cc/ Cd/ Ce/
E0 E1 E2 F0 F1 F2
Figure 16. CS8414 Block Diagram
20
M3 M2 M1 M0
17 18 24 23
Audio
Serial
Port
R
e
g
i
s
t
e
r
s
11
FSYNC
12
SCK
26
SDATA
1
C
14
U
28
VERF
15
CBL
25
ERF
DS240F1

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