GM16C550 Ver la hoja de datos (PDF) - Hynix Semiconductor

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GM16C550

ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFOs

Hynix Semiconductor 

GM16C550

Timing Waveforms (continued)

RAVR FIFO First byte (This Sets RDR)

SIN

DATA (5-6)

STOP

SAMPLE CLOCK

TRIGGER LEVEL

INTERRUPT

(FCR6,7 = 0.0)

LSI INTERRUPT

NOTE 2

tSINT

tRINT

tRINT

FIFO OR

ABOVE TRIGGER LEVEL

FIFO BELOW

TRIGGER LEVEL

RD, RD

(RDLS

RD, RD

(RDRBR)

ACTIVE

ACTIVE

RCVR FIFO Byte Other Than the First Byte (RDR is Already Set)

SIN

SAMPLE CLOCK

TIMEOUT OR

TRIGGER LEVEL

INTERRUPT

LSI INTERRUPT

RD, RD

(RDLSR)

NOTE 2

tSINT

TOP BYTE OF FIFO

tSINT

tRINT

ACTIVE

FIFO AT OR

ABOVE TRIGGER LEVEL

(FIFO BELOW

tRINT TRIGGER LEVEL)

RD, RD

(RDRBR)

ACTIVE

PREVIOUS BYTE

READ FROM FIFO

ACTIVE

Receiver Ready (pin 29) FCRO = 0 or FCRO = 1 and FCRO = 3 (Mode 0)

RD, RD

(RDRBR)

ACTIVE

NOTE 1

SIN

STOP

(FIRST BYTE)

SAMPLE CLK

RXRDY

tSINT

NOTE 2

Note 1: This is the reading of the last byte in the FIFO

Note 2: If FCRO =1, then Tsint = 3 RCLKs. For a timeout tSINT = 0 RCLKs.

8

tRINT

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