M46 Ver la hoja de datos (PDF) - Conexant Systems
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M46 Datasheet PDF : 47 Pages
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M46
Baseband Processor
Table 3. EXB Timing Specifications
Parameter
Access time
Address bus hold time after read strobe
Chip select hold time after read strobe
Duration of read strobe
Data bus hold time after write strobe
Access time
Address bus hold time after read strobe
Chip select hold time after read strobe
Duration of write strobe
Data bus hold time after write strobe
Access time
Address bus hold time after read strobe
Chip select hold time after read strobe
Duration of read strobe
Data bus hold time after write strobe
Access time
Address bus hold time after read strobe
Chip select hold time after read strobe
Duration of write strobe
Data bus hold time after write strobe
Note 1: WS is the number of wait states.
Symbol
Min
Read Timing for 0 Wait States
T_access
T_addr_hold
T_cs_hold
T_oen
T_data_hold
0
Write Timing for 0 Wait States
T_access
T_addr_hold
T_cs_hold
T_wen
T_data_hold
Read Timing for 1 or More Wait States
T_access
T_addr_hold
T_cs_hold
T_oen
T_data_hold
0
Write Timing for 1 or More Wait States
T_access
T_addr_hold
T_cs_hold
T_wen
T_data_hold
Max (Note 1)
Units
45
ns
6
ns
6
ns
20
ns
ns
43
ns
4
ns
5
ns
20
ns
34
ns
WS × 51 + 25
ns
24
ns
2
ns
WS × 51
ns
ns
WS × 51 + 25
ns
4
ns
1
ns
WS × 51 – 1
ns
30
ns
14
June 14, 2000
Table 4. Chip Select Configuration Register
Bit
Name
Function
15:9
Reserved
N/A
8:7
DELAY
Assertion of the chip select will be asserted this many cycles after the
address is stable. This allows for peripherals that require extra
address bus settling time.
6
POLARITY
Chip select polarity:
1 = active high
0 = active low
5:4
SIZE[1:0]
Data bus width:
00 = byte
01 = half word
10 = word
11 = undefined
3:1
WAIT[2:0]
Number of wait states. Maximum is seven.
0
ENABLE
Chip select enable:
0 = disabled
1 = enabled
Conexant
Proprietary Information and Specifications are Subject to Change
100779C
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