M46 Ver la hoja de datos (PDF) - Conexant Systems
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M46 Datasheet PDF : 47 Pages
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M46
Baseband Processor
Bit
29:31
28
27
26
25
24
23
22
21
20
19
18
Source
Reserved
GPIO port B[6]
GPIO port B[1]
GPIO port B[7]
Reserved
Keypad (key pressed)
GPIO port B[4]
GPIO port B[5]
GPIO port B[3]
Debug port Rx
Autobaud interrupt
Debug port Tx
17 GPIO port B[0]
16 SDS port Rx
15 SDS_Rx (start bit received)
Table 6. Interrupt Pending Register Sources
Internal/External
External
External
External
Internal
External
External
External
Internal
Internal
Internal
External
Internal
Internal
Bit
Source
14 SDS port transmit
13 DSP
12 DMA channel 4, SIM Rx and Tx
11 DMA channel 3, debug Tx
10 DMA channel 2, SDS Tx
9
DMA channel 1, debug Rx
8
DMA channel 0, SDS Rx
7
GPIO port B[2]
6
Reserved
5
SIM interrupt
4
RTC alarm
3
PTGB (generates baud rate for
debug port)
2
PTGA (generates baud rate for
SDS port)
1
Timer B (used for general timing)
0
Timer A (used for SIM timing)
Internal/External
Internal
Internal
Internal
Internal
Internal
Internal
Internal
External
Internal
Internal
Internal
Internal
Internal
Internal
IRQ Interrupt Register. The IRQ Interrupt Register contains
bits for all the possible interrupt sources. The IRQ Interrupt
Register bits have the same mapping to the interrupt sources as
the Interrupt Pending Register (see Table 6). If a bit for a
particular interrupt is set to 1, the following conditions apply to
that interrupt:
• The interrupt has occurred
• The interrupt is enabled
• The interrupt is set to generate an IRQ interrupt
If the bit is set to 0, at least one of the conditions listed above is
not met.
Timers
The BP timer block contains the following timers:
• Two general purpose timers (Timer A and Timer B)
• Two precision timing generators (PTG A and PTG B)
General Purpose Timers ______________________________
There are two 16-bit general purpose counters/timers used to
generate time related interrupts to the ARM. Timer A is used to
generate timeouts related to the SIM interface (required by the
ETSI GSM specifications). Timer A uses either the SIM system
clock or the SIM Elementary Time Unit (ETU) clock as an input
clock. The output from Timer A is input to the Interrupt
Controller.
Timer B is used for general purpose timing. Its input clock can
be either the system clock (3.9 MHz) or the ARM clock (19.5
MHz). The output from Timer A is input to the Interrupt
Controller as timb_irq.
Each of the timers consists of a Latch Register and a Counter
Register. The Counter Register is loaded from the Latch
Register and the timer counts down the contents of the Counter
Register. When the Counter Register contents reach 0, the
interrupt is generated.
Registers for General Purpose Timers. The address and
default values for the General Purpose Timers Registers are
specified in Table 2.
Timer Mode Register. Each of the timers has a dedicated
Timer Mode Register. The contents of this register determine
the configuration of the timer. The function of each bit in the
register is provided in Table 7.
Latch Register. Each of the timers has a dedicated Latch
Register. The contents of this register are loaded into the
counter.
Counter Register. Each of the timers has a dedicated Counter
Register. Writing to this register also writes the data to the Latch
Register.
16
June 14, 2000
Conexant
Proprietary Information and Specifications are Subject to Change
100779C
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