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ST755 Ver la hoja de datos (PDF) - STMicroelectronics

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Lista de partido
ST755 Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
ST755
APPLICATION CIRCUIT
To achieve the best performances from switching
power supply topology, particular care to layout
drawing is needed, in order to minimize EMI and
obtain low noise, jitter free operation moreover, it
ensures the full device functionality. Layout
design proposed on demoboard (see picture 2)
helps to lower the developing time.
Figure 1: TYPICAL APPLICATION CIRCUIT
Wire lengths must be minimized, filter and
by-pass capacitors C1, C2 and C3 must be low
ESR type, placed as close possible to the
integrated circuit. The 10µH inductor must be
chosen built on a core, taking care that saturation
current should be higher than the peak LX switch
current. See the PEAK INDUCTOR CURRENT
vs. LOAD CURRENT graph ( figure 6)
(*) R1 and R2 can be omitted for Iout<200mA.
(**) C6: Very low noise but poor transient and load response speed.
(***) C3 (alternative to C6): faster transient and load response.
Figure 2: Printed Demoboard
Component Values
Capacitor
C1
C2
C3
C4
C5
C6
4/9
Value
47
100
82
1
10
47
Unit
Resistor
µF
R1
µF
R2
pF
R3
µF
R4
µF
R5
pF
Symbol Pin
V CC
1
Vout
2
SHDN
3
GND
4
Value
Unit
130
K
300
K
10
K
40.7
K
10
K

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