STLC2500 Ver la hoja de datos (PDF) - STMicroelectronics
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STLC2500 Datasheet PDF : 23 Pages
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STLC2500
3.4 Clock specifications
The STLC2500 supports, on the same input pin, the system clock both as a sine wave clock and as a dig-
ital clock (see table 15 for selection). The system clock section is powered by VDD_CLD (G08 and H09).
The voltage range for VDD_CLD is the same as for VDD_IO_A.
Table 6. System clock supported frequencies
Symbol
Parameter
FIN
Clock input frequency list
Values
13, 26, 19.2, 38.4
Unit
MHz
Table 7. System clock overall specifications
Symbol
Parameter
FINTOL Tolerance on input frequency
Min.
Typ.
Max.
Unit
-20
20
ppm
Table 8. System clock, sine wave specifications
Symbol
VPP
NH
ZINRe
Parameter
Peak to peak voltage range
Total harmonic content of input signal
Real part of parallel input impedance at pin
Min.
Typ.
Max.
Unit
0.2
0.5
1
V
-25
dBc
30
60
90
KΩ
Table 9. System clock, digital clock DC specifications
Symbol
VIL
Parameter
Low Level input voltage
VIH
High Level input voltage
Min.
0.85 *
VDD_IO_A
Typ.
Max.
Unit
0.22 *
V
VDD_IO_A
V
Table 10. System clock, digital clock AC specifications
Symbol
TRISE
TFALL
DCYCLE
Parameter
10%-90% rise time
90%-10% fall time
Duty Cycle
Min.
45
Typ.
1,5
1,5
50
Max.
6
6
55
Unit
ns
ns
%
Table 11. Low Power clock specifications
The low power clock pin is powered by connecting VDD_IO_B to the wanted supply.
Symbol
Duty Cycle
Accuracy
Parameter
Min.
30
Typ.
Max.
Unit
70
%
±250
ppm
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