STLC2500 Ver la hoja de datos (PDF) - STMicroelectronics
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STLC2500 Datasheet PDF : 23 Pages
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STLC2500
5 PINOUT
5.1 Pin out bottom view
10
9
8
7
6
ANA_1
ABUS_
QP_IP
ABUS_
IN_QN
VSS_RF
RFN
A
5
4
3
2
1
RFP
VSS_RF VDD_HV VSS_ANA VSS_DIG
ABUS_
VSS_ANA VSS_ANA QN_IN
B
ABUS_
IP_QP
VSS_ ANA VDD_RF
ANA_2
VSS_ANA VDD_DIG JTAG_TDO
ANA_3
VDD_HV VSS_ANA VSS_ANA
VDD_T
VSS_ANA VSS_ANA VDD_DIG
JTAG_
NTRST
JTAG_TDI
C
VDD_HV ANA_4 VSS_ANA
D
VDD_DSM VSS_ANA VSS_ANA
E
VDD_N VDD_HV VSS_ANA
F
VSS_DIG JTAG_TCK JTAG_TMS
VSS_DIG PCM_SYNC PCM_CLK
VDD_IO_A PCM_A PCM_B
VDD_CL VSS_ANA VDD_CLD
VSS_DIG VDD_IO_A VDD_IO_A
G
CONFIG
RF_CLK_IN VDD_CLD VSS_DIG VSS_DIG VSS_DIG VSS_DIG VSS_DIG
_R
CONFIG
_CLK
CONFIG
_JS
H
VDD_DIG GPIO_2 GPIO_0
UART_
RXD
UART_
CTS
HOST_
WAKEUP
CONFIG
_RF
BT_
WAKEUP
VDD_DIG
CONFIG
_M
J
AF_PRG GPIO_3 PGIO_1
UART_
TXD
UART_
RTS
LP_CLK VDD_IO_B RESETN
VDD_D
VDD_HV
K
5.2 Pin Description and Assignment
Table 13 shows the pin list of the STLC2500. The column "PU/PD" shows the pads implementing a pull-
down/up. The column "DIR" describes the pin directions:
– I for Inputs
– O for Outputs
– I/O for Input/Output
– O/t for tri-state outputs
The column Reset and Default show the state of the pins in reset and the default value after reset. For the
output pin the default drive capability is 2 mA.
Table 13. STLC2500 pin list (Functional and Supply)
Name
Pin #
Description
Clock and Reset pins
RESETN
K03
RF_CLK_IN
H10
LP_CLK
K05
Global reset - active low
Reference clock input
Low power clock input
DIR
Reset
Default
after reset
VDD_
IO_x
I
Input
Input
A
I
Input
Input
(3)
I
Input
Input
B
5/23
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