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MD82C288-10

BUS CONTROLLER FOR M80286 PROCESSORS

Intel 

M82C288

are immediately forced inactive When CEN makes a

LOW to HIGH transition the commands and DEN

outputs immediately go to the appropriate state (see

timing waveforms) READY must still become active

to terminate a bus cycle if CEN remains LOW for a

selected bus controller (CENL was latched HIGH)

Some memory or I O systems may require more ad-

dress or write data setup time to command active

than provided by the basic command output timing

To provide flexible command timing the CMDLY in-

put can delay the activation of command outputs

The CMDLY input must be sampled LOW to activate

the command outputs CMDLY does not affect the

control outputs ALE MCE DEN and DT R

Figure 12 System Use of AEN and CENL

271077 – 12

11

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