STW51000 Ver la hoja de datos (PDF) - STMicroelectronics
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STW51000 Datasheet PDF : 8 Pages
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GreenSIDE - STW51000
The GreenSIDE bus architecture is based on the Multi-Layer AHB (Transfer Cross Bar). This bus archi-
tecture provides a large amount of bandwidth in the system, and prevents the bus architecture from being
a bottleneck.
A 16Mbit memory provides a data exchange capability between CPUs. It allows storage of a collection of
data coming from Fast Serial Ports or other DMA-based peripherals.
6 ST140 Overview
The ST140 is a 32-bit MCU/16-bit DSP Load/Store architecture, which provides full DSP-MCU capability.
This capability is hosted by a comprehensive 32-bit Instruction set plus a 16-bit Instruction set for high
code density, and a specific instruction mode offering an increased level of parallelism suitable for high
performance DSP operations. The ST140 architecture is designed for maximum code efficiency for both
micro-controller code and vector DSP code, even when programmed with "C" Language. The 32 x 40-bit
data registers correspond to "C" data types and allow high precision results. The 17 x 32-bit Pointer / Index
registers provide easy data access and the 3 hardware loop controllers are managed using C. The ST140
Compiler checks for parallel arguments at the instruction level, checks blocks of code, determines critical
paths and dependencies and re-orders instructions to benefit from the predication and to maximize speed.
The ST140 is fully pipelined for maximum efficiency; while data accesses are access decoupled for mini-
mum access latency and reduced need to use the Data Registers. ST140 includes a 32Kbytes Program
and 64 Kbytes Data Cache for high performance execution.
Table 2. ST140 Benchmarks
Functions
Formula
N
B
Real Block IFR
(T+1) x N/4 + 24
40
Simple-Sample FIR
T/4 + 14
1
Complex Block FIR
(T + 0.5) x N + 13
40
LMS
T/2 + 16
1
IIR
N/A
1
2
Vector Dot Product
N/4 + 11
40
Vector Add
N / 2 + 11
40
Vector Maximum
N/4+10
40
FFT Radix-4
-
256
N : Nb of Points - B: Nb of Sections - T: Nb of Taps - M: Nb of New Relative Maxima
T
M
Cycles
16
194
16
18
16
673
16
28
8
21
31
5
20
1380
7 ARM Sub-System Overview
The GreenSIDE ASSP is based on the open ARM PrimeXSys™ platform built around the ARM926 core
and includes a set of Peripherals and an AMBA Multi-Layer AHB system bus for maximized throughput.
The ARM Sub System contains a set of standard Peripherals including Timers, Watchdog, 32-bit GPIOs,
and Clock/System Controller.
Beside the standard peripherals the ARM Sub system also contains a set of high-speed DMA Peripherals
including Multi-Channel Serial Ports, UTOPIA interface, Turbo Decoder Engine and Convolutional Decod-
er Engine.
Three DMA Engine manage all DMA operations over the System. An Interrupt Controller with 32 standard
interrupts and 16-vectored interrupts provides a simple software interface to the interrupt system. For ex-
pansion purpose, two External Memory Controllers can address SRAM, Flash, ROM or I/O Devices.
Those External Devices can be accessed by either DSPs or MCU.
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