CMX673E3 Ver la hoja de datos (PDF) - CML Microsystems Plc
Número de pieza
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Lista de partido
CMX673E3 Datasheet PDF : 14 Pages
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1.3 Signal List
Package
D4
E3
P1
Signal
Description
Pin
Pin
Pin
No.
No.
No.
Name
2
3
1
XTAL/CLOCK
4
5
2
5
7
3
XTALN
ENABLE
7
8
4
10
13
5
DETECT
SIGIN
12
15
6
14
17
7
VSS
VREF
15
18
8
VDD
1, 3, 6, 1, 2, 4,
NC
8, 9, 6, 9,
11, 13, 10, 11,
16 12, 14,
16, 19,
20
Notes: I/P = Input
O/P = Output
BI = Bidirectional
Type
I/P
O/P
I/P
O/P
I/P
Power
O/P
Power
The input to the on-chip oscillator and external
clock input. Components are on chip.
The inverted output of the on-chip oscillator.
A logic ‘1’ applied to this input enables the
DETECT output. A logic ‘0’ will reset
DETECT output to a logic ‘0’.
When a call progress signal is detected, this
output goes to a logic ‘1’.
Signal input. Signals to this pin should be ac
coupled. The dc bias of this pin is set
internally.
The negative supply rail (ground).
Internally generated reference voltage, held at
½VDD.
The positive supply rail. This pin should be
decoupled to VSS by a capacitor.
Internal Connection. Do not make any
connection to these pins.
© 2001 Consumer Microcircuits Limited
4
D/673/5
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