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TDA9950

CEC/I2C-bus translator

NXP Semiconductors. 

NXP Semiconductors

TDA9950

CEC/I2C-bus translator

8.4 Register descriptions

Table 6. APR - Address Pointer Register (address 00h) bit description (Write mode)

Bit

Symbol

Description

7 to 5 reserved

reserved (must be set to 000)

4 to 0 REG_PTR[4:0]

Address Pointer: Address of the register that will be

read/written during further I2C-bus communication.

Table 7. CSR - TDA9950 Status Register (address 00h) bit description (Read mode)

Bit

Symbol

Description

7

BUSY

BUSY:

0 = the TDA9950 is able to handle requests.

1 = the TDA9950 is busy and cannot accept any further

request.

6

INT

INT:

0 = the INT interrupt output is inactive.

1 = the INT interrupt output is active.

5

ERR

ERR:

0 = no error.

1 = an error occurred (specified in the TDA9950 Error

Register). Cleared by a read of the TDA9950 Error Register.

4 to 0 -

not used

Table 8. CER - TDA9950 Error Register (address 01h) bit description (Read only)

Bit

Symbol

Description

7 to 0 CER[7:0]

TDA9950 Error Register: This register provides details of the

last error that occurred. Reading this register resets the ERR

bit in the TDA9950 Status Register.

00h = no error has occurred since reset.

01h = watchdog reset has occurred.

02h = long CEC message with no End Of Message (EOM)

detected.

03h = CEC overrun - no buffer available to receive.

Table 9. CVR - TDA9950 Version Register (address 02h) bit description (Read only)

Bit

Symbol

Description

7 to 4 CVR_MAJ[3:0]

TDA9950 major version register: Major version

3 to 0 CVR_MIN[3:0]

TDA9950 minor version register: Minor version

TDA9950_2

Product data sheet

Rev. 02 — 22 October 2009

© NXP B.V. 2009. All rights reserved.

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