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PI6C110EV

Clock Solution for 133 MHz Celeron/Pentium II/III Processors

Pericom Semiconductor 

PI6C110E

Clock Solution for 133 MHz

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I2C Considerations

1. Address Assignment: Any clock driver in this specification can use the single, 7 bit address shown below. All devices can use

the address if only one master clock driver is used in a design.

The following address was confirmed by Philips on 09/04/96.

A6 A5 A4 A3 A2 A1 A0

1

1

0

1

0

0

1

R/W#

0

Note:

The R/W# bit is used by the I2C controller as a data direction bit. A “zero” indicates a transmission (WRITE) to the clock device.

A ‘one’ indicates a request for data (READ) from the clock driver. Since the definition of the clock buffer only allows the controller

to WRITE data; the R/W# bit of the address will always be seen as a “zero.”

2. Slave/Receiver: The clock driver is assumed to require only slave/receiver functionality.

3. Data Transfer Rate: 100 kbits/s (standard mode) is the base functionality.

4. Logic Levels: Assume all devices are based on a 3.3 Volt supply.

5. Data Byte Format: Byte format is 8-bits.

6. Data Protocol:

To simplify the clock I2C interface, the clock driver serial protocol was specified to use only block writes from the controller.

The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte

has been transferred. Indexed bytes are not allowed.

The clock driver must meet this protocol which is more rigorous than previously stated I2C protocol. Treat the description from

the viewpoint of controller. The controller “writes” to the clock driver and if possible would “read” from the clock driver.

“The block write begins with a slave address and a write condition. After the command code the host (controller) issues a byte

count which describes how many more bytes will follow in the message. If the host had 20 bytes to send, the first byte would

be the number 20 (14h), followed by the 20 bytes of data. The byte count may not be 0. A block write command is allowed

to transfer a maximum of 32 data bytes.”

1 bit

Start bit

7 bits

1

Slave Address R/W

1

8 bits

1

Ack Command Code Ack

Byte Count = N

Ack Data Byte 1 Ack Data Byte 2

1 bit 8 bits

1 8 bits

Ack ... Data Byte N

1

8 bits

Note: The acknowledgment bit is returned by the slave/receiver (the clock driver).

Ack Stop

1

1

12

PS8410

08/11/99

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