GTLP16612A Ver la hoja de datos (PDF) - Pericom Semiconductor
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GTLP16612A Datasheet PDF : 8 Pages
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GTLP16612A
CMOS 18-Bit TTL/GTLP
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Pin Descriptions
Pin Names
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
CLKAB
CLKBA
VREF
A1-A18
B1-B18
Description
A-to-B Output Enable (Active LOW)
B-to-A Output Enable (Active LOW)
A-to-B Clock Enable (Active LOW)
B-to-A Clock Enable (Active LOW)
A-to-B Latch Enable (Transparent HIGH)
B-to-A Latch Enable (Transparent HIGH)
A-to-B Clock Pulse
B-to-A Clock Pulse
GTLP Input Reference Voltage
A-to-B TTL Data Inputs or
B-to-A 3-State Outputs
B-to-A GTLP Data Inputs or
A-to-B Open Drain Outputs
Functional Description
The PI74GTLP16612A combines a universal transceiver function with a TTL to GTLP translation. The A-Port and control pins operate
at LVTTL or 5V TTL levels while the B-Port operates at GTLP levels. The transceiver logic includes D-type latches and D-type flip-flops
to allow data flow in transparent, latched, and clock mode. The functional operation is described below:
Truth Table(1)
Inputs
CEAB
OEAB
LEAB
CLKAB
A
X
H
X
X
X
L
L
L
H
X
L
L
L
L
X
X
L
H
X
L
X
L
H
X
H
L
L
L
↑
L
L
L
L
↑
H
H
L
L
X
X
Notes:
1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA,
LEBA, CLKBA, and CEBA.
2. Output level before indicated steady-state input conditions were estab-
lished, provided CLKAB was HIGH before LEAB went LOW.
3. Output level before indicated steady-state input conditions were estab-
lished.
Output B
Z
B0(2)
B0(3)
L
H
L
H
B0(3)
Mode
Latched
Storage
of A Data
Transparent
Clocked Storage
of A Data
Clock Inhibit
2
PS8431 09/24/99
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