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UPD72870AF1

IEEE1394 1-CHIP OHCI HOST CONTROLLER

NEC => Renesas Technology 

µPD72870A

3.1.21 Offset_60 Cap_ID & Next_Item_Ptr Register

The Cap_ID signals that this item in the Linked List is the registers defined for PCI Power Management, while the

Next_Item_Ptr describes the location of the next item in the µPD72870A’s Capability List.

Bits

7-0

15-8

R/W

Description

R

Cap_ID Constant value of 01H. The default value identified the Link List item as being the PCI

Power Management registers, while the ID value is assigned by the PCI SIG.

R

Next_Item_Ptr Constant value of 00H. It indicated that there are no more items in the Link

List.

3.1.22 Offset_62 Power Management Capabilities Register

This is a 16-bit read-only register that provides information on the power management capabilities of the

µPD72870A.

Bits

2-0

3

4

5

8,6

9

10

15-11

R/W

Description

R

version Constant value of 001. The power management registers are implemented as defined

in revision 1.0 of PCI Bus Power Management Interface Specification.

R

PME clock Constant value of 0.

R

Auxiliary power source Constant value of 0. The alternative power source is not supported.

R

DIS Constant value of 0.

R

Reserved Constant value of 000.

R

D1_support Constant value of 0. The µPD72870A does not support the D1 Power

Management state.

R

D2_support Constant value of 1. The µPD72870A supports the D2 Power Management state.

R

PME_support Constant value of 01100.

28

Preliminary Data Sheet S14653EJ1V0DS00

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