MOSEL VITELIC
V58C2256(804/404/164)S
V 58 C
MOSEL VITELIC
MANUFACTURED
2 256(80/40/16) 4
DDR SDRAM
CMOS
2.5V
256Mb, 8K Refresh
x8, x4, x16
S X T XX
SPEED
6 (133MHz@CL2.5))
7 (143MHz@CL2.5))
75(133MHz@CL2.5)
8 (125MHz@CL2.5)
COMPONENT
PACKAGE, T = TSOP S=SOC BGA
COMPONENT
REV LEVEL A=0.14u
SSTL
4 Banks
Block Diagram
Column address
counter
64M x 4
Column Addresses
A0 - A9, A11, AP, BA0, BA1
Row Addresses
A0 - A12, BA0, BA1
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Bank 0
8192 x 1024
x8
Row decoder
Memory array
Bank 1
8192 x 1024
x8
Row decoder
Memory array
Bank 2
8192 x 1024
x8
Row decoder
Memory array
Bank 3
8192 x 1024
x8
CK, CK
DQS
Input buffer Output buffer
DLL
Strobe
Gen.
DQ0-DQ3
Data Strobe
Control logic & timing generator
V58C2256(804/404/164)S Rev. 1.4 October 2002
4