V58C2256804SXT7 Ver la hoja de datos (PDF) - Mosel Vitelic Corporation
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V58C2256804SXT7 Datasheet PDF : 61 Pages
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MOSEL VITELIC
V58C2256(804/404/164)S
Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs
CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to
make DDR SDRAM useful for a variety of different applications. The default value of the mode register is not
defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation.
The mode register is written by asserting low on CS, RAS, CAS, WE and BA0 (The DDR SDRAM should be
in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins
A0 ~ A12 in the same cycle as CS, RAS, CAS, WE and BA0 low is written in the mode register. Two clock
cycles are required to meet tMRD spec. The mode register contents can be changed using the same com-
mand and clock cycle requirements during operation as long as all banks are in the idle state. The mode reg-
ister is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode
uses A3, CAS latency (read latency from column address) uses A4 ~ A6. A7 is a Mosel Vitelic specific test
mode during production test. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Refer
to the table for specific codes for various burst length, addressing modes and CAS latencies.
1. MRS can be issued only at all banks precharge state.
2. Minimum tRP is required to issue MRS command.
BA1 BA 0
A 12
to
A3
A2 A1 A0 Address Bus
0 MRS
RFU : Must be set "0"
QFC I/O DLL Extended Mode Register
0 MRS
RFU
DLL TM CAS Latency BT Burst Length
Mode Register
A8 DLL Reset
A7
mode
0
No
0
Normal
1
Yes
1
Test
A3 Burst Type
0 Sequential
1 Interleave
CAS Latency
Burst Length
BA0
An ~ A0
0
(Existing)MRS Cycle
A6 A5 A4 Latency
0 0 0 Reserve
A2 A1 A0
1
Extended Funtions(EMRS)
0 0 1 Reserve
000
01 0
2
001
01 1
3
010
1 0 0 Reserve
011
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
10
11
11
1 Reserve
0
2.5
1 Reserve
100
101
110
111
A1 I/O Strength
0
Full
1
Half
A0 DLL Enable
0
Enable
1
Disable
Latency
Sequential Interleave
Reserve
Reserve
2
2
4
4
8
8
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
A2 QFC Control
0
Disable
1
Enable
Mode Register Set
0
1
2
3
4
5
6
7
8
CK, CK
Command
Precharge
All Banks
tCK
tRP *2
*1
Mode
Register Set
tMRD
Any
Command
V58C2256(804/404/164)S Rev. 1.4 October 2002
8
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