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W83195BR-101

Winbond Clock Generator For Intel 915/925 Chipsets

Winbond 

W83195BR/G-101

STEPLESS FOR INTEL 915/925 CHIPSETS

7.6 Register 5: Watchdog Control (Default: 02h)

BIT

NAME

PWD

DESCRIPTION

TYPE

7 Reserved

6 EN_WD

5 WD_TIMEOUT

4 SAF_FREQ [4]

3 SAF_FREQ [3]

2 SAF_FREQ [2]

1 SAF_FREQ [1]

0 SAF_FREQ [0]

X Reserved

R/W

Program this bit =>

1: Enable Watchdog Timer feature.

0: Disable Watchdog Timer feature.

0

R/W

Read-back this bit =>

During timer count down the bit read back to 1.

If count to zero, this bit read back to 0.

Read Back only. Timeout Flag. This bit is Read Only.

0 1: Watchdog has ever started and counts to zero.

R

0: Watchdog is restarted and counting.

0

R/W

0

0

These bits will be reloaded in Reg-0 to select frequency

table. As the watchdog is timeout and EN_SAFE_FREQ=1.

1

0

7.7 Register 6: SRC Control (1 = Enable, 0 = Stopped) (Default: FEh)

BIT

NAME

7 Reserved

6 33,32

5 31,30

4 26,27

3 24,25

2 22,23

1 19,20

0 Reserved

PWD

1

1

1

1

1

1

1

0

DESCRIPTION

Reserved

SRCT/C 6 outputs control

SRCT/C 5 outputs control

SRCT/C 4_SATA outputs control

SRCT/C 3 outputs control

SRCT/C 2 outputs control

SRCT/C 1 outputs control

Reserved

TYPE

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

7.8 Register 7: Winbond Chip ID (Default: 22h) (Read Only)

BIT

NAME

PWD

DESCRIPTION

7 CHPI_ID [7]

0 Winbond Chip ID. W83195BR/G-101

6 CHPI_ID [6]

0 Winbond Chip ID.

5 CHPI_ID [5]

1 Winbond Chip ID.

TYPE

R

R

R

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