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W83195BR-101

Winbond Clock Generator For Intel 915/925 Chipsets

Winbond 

W83195BR/G-101

STEPLESS FOR INTEL 915/925 CHIPSETS

7.15 Register 14: Control (Default: 10h)

BIT

NAME

PWD

DESCRIPTION

TYPE

7 DRI_CONT

CPUT / SRCT / DOT_T output state in during POWER

DOWN assertion.

1: Driven (2*Iref), 0: Tristate (Floating)

0

CPUT / SRCT / DOT_T output state in during STOP Mode

assertion.

R/W

1: Driven (6*Iref), 0: Tristate (Floating)

Complementary parts always tri-state (floating) in power

down or stop mode.

6 Reserved

0 Reserved

R/W

5 SPCNT [5]

0

R/W

4 SPCNT [4]

1

R/W

3 SPCNT [3]

2 SPCNT [2]

0 Spread Spectrum Programmable time, the resolution is

R/W

0 280ns. Default period is 11.8us

R/W

1 SPCNT [1]

0

R/W

0 SPCNT [0]

0

R/W

7.16 Register 15: Reserved (Default: ECh)

7.17 Register 16: Skew Control (Default: E4h)

BIT

NAME

PWD

DESCRIPTION

7 Reserved

1 Reserved

6 Reserved

1 Reserved

5 Reserved

1

4 Reserved

0 Reserved

3 Reserved

0

2 PSKEW [2]

1 PSKEW [1]

0 PSKEW [0]

1 CPU1 to PCI skew control, Skew resolution is 300ps

0 The decision of skew direction is same as PSKEW [2:0]

0 setting

TYPE

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

7.18 Register 17: Reserved (Default: 00h)

7.19 Register 18: Reserved (Default: 00h)

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