HSP50110(1999) Ver la hoja de datos (PDF) - Intersil
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HSP50110 Datasheet PDF : 24 Pages
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HSP50110
CLK by a programmable factor of 2, 4, or 8. When the
programmable clock factor is 1, IOUT9 is pulled high, and the
CLK signal should be used as the clock. The beginning of a
serial data word is signaled by the assertion of DATARDY one
serial clock before the first bit of the output word. In I followed
by Q Mode, DATARDY is asserted prior to each 16-bit data
word. For added flexibility, the Formatter may be configured to
output the data words in either MSB or LSB first format.
IOUT9
DATARDY
IOUT0/
QOUT0
LSB
MSB
DATARDY LEADS 1st BIT
LSB
NOTE: Assumes data is being output LSB first.
FIGURE 15. SERIAL TIMING (SIMULTANEOUS I/Q MODE)
IOUT9
DATARDY
IOUT0
MSB
LSB 0
1 MSB
I DATA WORD
Q DATA
DATARDY
LEADS 1st BIT
WORD
I OUTPUT IDENTIFIED
BY 1 IN LSB OF DATA WORD
NOTE: Assumes data is being output MSB first.
DATARDY may be programmed active high or low.
FIGURE 16. SERIAL TIMING (I FOLLOWED BY Q MODE)
Gain Distribution
The gain distribution in the DQT is shown in Figure 17. These
gains consist of a combination of fixed, programmable, and
adaptive gains. The fixed gains are introduced by processing
elements like the Synthesizer/Mixer and CIC Filter. The
programmable and adaptive gains are set to compensate for
the fixed gains as well as variations in input signal strength.
The bit range of the data path between processing elements
is shown in Figure 17. The quadrature inputs to the data path
are 10-bit fractional two’s complement numbers. They are
multiplied by a 10-bit quadrature sinusoid and rounded to
12-bits in the Synthesizer/Mixer. The I and Q legs are then
scaled by a fixed gain of 2-36 to compensate for the worst
case gain of the CIC filter. Next, a gain block with an adaptive
and programmable component is used to set the output signal
level within the desired range of the 10-bit output (see Setting
DQT Gains Section). The adaptive component is produced by
the AGC and has a gain range from 1.0 to 1.9375*27. The
programmable component sets the gain range of the CIC
shifter which may range from 20 to 263. Care must be taken
when setting the AGC gain limits and the CIC Shifter gain
since the sum of these gains could shift the CIC Scaler output
beyond the bit range (-28 to 2-46) of the CIC Filter input. The
CIC Filter introduces a gain factor given by RN where R is the
decimation rate of the filter and N is the CIC order. The CIC
order is either 1 (integrate and dump filter) or 3. Depending on
configuration, the CIC Filter introduces a gain factor from 20 to
236. The output of the CIC Filter is then rounded and limited to
an 11-bit window between bit positions 21 to 2-9. Values
outside this range saturate to these 11 bits. The
Compensation Filter introduces a final gain factor of 1.0, 0.65,
AGC GAIN
MANTISSA EXPONENT CIC BARREL
1.0 - 1.9375
(0.0625 STEPS)
20-27
SHIFTER
20-263
SYNTHESIZER/
MIXER
G = 0.9990
CIC
SCALER
G = 2-36
G = 1.0 - 1.9375*270
CIC
FILTER
G = 20- 236
(RN)
COMPENSATION
FILTER
GAIN
G = 1.0, 0.65, 0.77
(BYPASS, x/sin(x), (x/sin(x))3
LIMIT
LIMIT
INPUT
GdB = 0dB
-20
2-1
GdB = -216.74dB
GdB = GAGC +
GSHIFTER
-21
20
BINARY POINT
2-1
-2-35
-28
GdB
=
=
20log[fS/fD]N
20log[R]N
-28
GdB = 0dB
GdB =
0dB BYPASS
-23
GdB
=
0dB
N = 1, 3
20
20
-21
-3.74dB
-2.27dB
20
20
-20
OUTPUT
2-1
2-1
2-1
2-1
2-1
2-9
2-10
G = -6.02dB RND
2-46
2-46
RND
2-9
2-9
2-9
2-9
RND
RND
BIT RANGE OF DATA PATH
FIGURE 17. GAIN DISTRIBUTION AND INTERMEDIATE BIT WEIGHTINGS
3-240
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